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authorVikram Kanigiri <vikram.kanigiri@arm.com>2014-03-11 17:41:00 +0000
committerDan Handley <dan.handley@arm.com>2014-03-21 17:17:48 +0000
commit6ba0b6d6743534b3d443602dc88558d62ea432b3 (patch)
tree4581ce3cd1104da70e38e8855ec35e824e5cb625 /plat
parent5132060c48fe2dbc3ce64755cd83b61d6e017f10 (diff)
downloadarm-trusted-firmware-6ba0b6d6743534b3d443602dc88558d62ea432b3.tar.gz
Remove partially qualified asm helper functions
Each ARM Trusted Firmware image should know in which EL it is running and it should use the corresponding register directly instead of reading currentEL and knowing which asm register to read/write Change-Id: Ief35630190b6f07c8fbb7ba6cb20db308f002945
Diffstat (limited to 'plat')
-rw-r--r--plat/fvp/aarch64/plat_common.c46
1 files changed, 32 insertions, 14 deletions
diff --git a/plat/fvp/aarch64/plat_common.c b/plat/fvp/aarch64/plat_common.c
index 1de6c03..d44ccb6 100644
--- a/plat/fvp/aarch64/plat_common.c
+++ b/plat/fvp/aarch64/plat_common.c
@@ -59,32 +59,43 @@ void enable_mmu()
mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,
ATTR_IWBWA_OWBWA_NTR_INDEX);
- write_mair(mair);
/*
* Set TCR bits as well. Inner & outer WBWA & shareable + T0SZ = 32
*/
tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA |
TCR_RGN_INNER_WBA | TCR_T0SZ_4GB;
+
+ /* Set TTBR bits as well */
+ ttbr = (unsigned long) l1_xlation_table;
+
if (GET_EL(current_el) == MODE_EL3) {
+ write_mair_el3(mair);
tcr |= TCR_EL3_RES1;
/* Invalidate EL3 TLBs */
tlbialle3();
+
+ write_tcr_el3(tcr);
+ write_ttbr0_el3(ttbr);
+
+ sctlr = read_sctlr_el3();
+ sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT | SCTLR_I_BIT;
+ sctlr |= SCTLR_A_BIT | SCTLR_C_BIT;
+ write_sctlr_el3(sctlr);
} else {
+
+ write_mair_el1(mair);
/* Invalidate EL1 TLBs */
tlbivmalle1();
- }
- write_tcr(tcr);
+ write_tcr_el1(tcr);
+ write_ttbr0_el1(ttbr);
- /* Set TTBR bits as well */
- ttbr = (unsigned long) l1_xlation_table;
- write_ttbr0(ttbr);
-
- sctlr = read_sctlr();
- sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT | SCTLR_I_BIT;
- sctlr |= SCTLR_A_BIT | SCTLR_C_BIT;
- write_sctlr(sctlr);
+ sctlr = read_sctlr_el1();
+ sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT | SCTLR_I_BIT;
+ sctlr |= SCTLR_A_BIT | SCTLR_C_BIT;
+ write_sctlr_el1(sctlr);
+ }
return;
}
@@ -92,10 +103,17 @@ void enable_mmu()
void disable_mmu(void)
{
unsigned long sctlr;
+ unsigned long current_el = read_current_el();
- sctlr = read_sctlr();
- sctlr = sctlr & ~(SCTLR_M_BIT | SCTLR_C_BIT);
- write_sctlr(sctlr);
+ if (GET_EL(current_el) == MODE_EL3) {
+ sctlr = read_sctlr_el3();
+ sctlr = sctlr & ~(SCTLR_M_BIT | SCTLR_C_BIT);
+ write_sctlr_el3(sctlr);
+ } else {
+ sctlr = read_sctlr_el1();
+ sctlr = sctlr & ~(SCTLR_M_BIT | SCTLR_C_BIT);
+ write_sctlr_el1(sctlr);
+ }
/* Flush the caches */
dcsw_op_all(DCCISW);