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authorSandrine Bailleux <sandrine.bailleux@arm.com>2013-11-28 09:43:06 +0000
committerDan Handley <dan.handley@arm.com>2013-12-05 11:33:15 +0000
commit65f546a14fbc0438c051b4243f71abd2206a7307 (patch)
tree1187ac9d3eb596ecb61ac4568969041392764a14 /plat
parent8d69a03f6a7db3c437b7cfdd15402627277d8cb4 (diff)
downloadarm-trusted-firmware-65f546a14fbc0438c051b4243f71abd2206a7307.tar.gz
Properly initialise the C runtime environment
This patch makes sure the C runtime environment is properly initialised before executing any C code. - Zero-initialise NOBITS sections (e.g. the bss section). - Relocate BL1 data from ROM to RAM. Change-Id: I0da81b417b2f0d1f7ef667cc5131b1e47e22571f
Diffstat (limited to 'plat')
-rw-r--r--plat/fvp/bl1_plat_setup.c10
1 files changed, 0 insertions, 10 deletions
diff --git a/plat/fvp/bl1_plat_setup.c b/plat/fvp/bl1_plat_setup.c
index 74b79d1..822a100 100644
--- a/plat/fvp/bl1_plat_setup.c
+++ b/plat/fvp/bl1_plat_setup.c
@@ -42,7 +42,6 @@
******************************************************************************/
extern unsigned long __COHERENT_RAM_START__;
extern unsigned long __COHERENT_RAM_END__;
-extern unsigned long __COHERENT_RAM_UNALIGNED_SIZE__;
extern unsigned long __BL1_RAM_START__;
extern unsigned long __BL1_RAM_END__;
@@ -56,8 +55,6 @@ extern unsigned long __BL1_RAM_END__;
*/
#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-#define BL1_COHERENT_RAM_LENGTH \
- (unsigned long)(&__COHERENT_RAM_UNALIGNED_SIZE__)
#define BL1_RAM_BASE (unsigned long)(&__BL1_RAM_START__)
#define BL1_RAM_LIMIT (unsigned long)(&__BL1_RAM_END__)
@@ -113,13 +110,6 @@ void bl1_early_platform_setup(void)
******************************************************************************/
void bl1_platform_setup(void)
{
- /*
- * This should zero out our coherent stacks as well but we don't care
- * as they are not being used right now.
- */
- memset((void *) BL1_COHERENT_RAM_BASE, 0,
- (size_t) BL1_COHERENT_RAM_LENGTH);
-
/* Enable and initialize the System level generic timer */
mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_EN);