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authorSandrine Bailleux <sandrine.bailleux@arm.com>2013-11-27 09:38:52 +0000
committerDan Handley <dan.handley@arm.com>2013-12-05 11:33:15 +0000
commit8d69a03f6a7db3c437b7cfdd15402627277d8cb4 (patch)
treea74ad7b72757ed85d084bf50ce20feb4164c2eb6 /plat/fvp/aarch64
parent3e850a84c94a5f1bc0141041ad32be94460716f7 (diff)
downloadarm-trusted-firmware-8d69a03f6a7db3c437b7cfdd15402627277d8cb4.tar.gz
Various improvements/cleanups on the linker scripts
- Check at link-time that bootloader images will fit in memory at run time and that they won't overlap each other. - Remove text and rodata orphan sections. - Define new linker symbols to remove the need for platform setup code to know the order of sections. - Reduce the size of the raw binary images by cutting some sections out of the disk image and allocating them at load time, whenever possible. - Rework alignment constraints on sections. - Remove unused linker symbols. - Homogenize linker symbols names across all BLs. - Add some comments in the linker scripts. Change-Id: I47a328af0ccc7c8ab47fcc0dc6e7dd26160610b9
Diffstat (limited to 'plat/fvp/aarch64')
-rw-r--r--plat/fvp/aarch64/bl1_plat_helpers.S2
-rw-r--r--plat/fvp/aarch64/fvp_common.c19
-rw-r--r--plat/fvp/aarch64/fvp_helpers.S2
3 files changed, 9 insertions, 14 deletions
diff --git a/plat/fvp/aarch64/bl1_plat_helpers.S b/plat/fvp/aarch64/bl1_plat_helpers.S
index 8cdb10e..0adb541 100644
--- a/plat/fvp/aarch64/bl1_plat_helpers.S
+++ b/plat/fvp/aarch64/bl1_plat_helpers.S
@@ -38,7 +38,7 @@
.globl plat_secondary_cold_boot_setup
- .section platform_code, "ax"; .align 3
+ .section .text, "ax"; .align 3
.macro platform_choose_gicmmap param1, param2, x_tmp, w_tmp, res
diff --git a/plat/fvp/aarch64/fvp_common.c b/plat/fvp/aarch64/fvp_common.c
index 0b5f4eb..fd0e073 100644
--- a/plat/fvp/aarch64/fvp_common.c
+++ b/plat/fvp/aarch64/fvp_common.c
@@ -367,8 +367,6 @@ static unsigned long fill_xlation_tables(meminfo *tzram_layout,
/*****************************************************************
* LEVEL3 PAGETABLE SETUP
- * The following setup assumes knowledge of the scatter file. This
- * should be reasonable as this is platform specific code.
*****************************************************************/
/* Fill up the level3 pagetable for the trusted SRAM. */
@@ -378,21 +376,13 @@ static unsigned long fill_xlation_tables(meminfo *tzram_layout,
if (tzram_end_index == tzram_start_index)
tzram_end_index++;
- /*
- * Reusing trom* to mark RO memory. BLX_STACKS follows BLX_RO in the
- * scatter file. Using BLX_RO$$Limit does not work as it might not
- * cross the page boundary thus leading to truncation of valid RO
- * memory
- */
+ /* Reusing trom* to mark RO memory. */
trom_start_index = FOUR_KB_INDEX(ro_start);
trom_end_index = FOUR_KB_INDEX(ro_limit);
if (trom_end_index == trom_start_index)
trom_end_index++;
- /*
- * Reusing dev* to mark coherent device memory. $$Limit works here
- * 'cause the coherent memory section is known to be 4k in size
- */
+ /* Reusing dev* to mark coherent device memory. */
dev0_start_index = FOUR_KB_INDEX(coh_start);
dev0_end_index = FOUR_KB_INDEX(coh_limit);
if (dev0_end_index == dev0_start_index)
@@ -506,6 +496,11 @@ void configure_mmu(meminfo *mem_layout,
unsigned long coh_start,
unsigned long coh_limit)
{
+ assert(IS_PAGE_ALIGNED(ro_start));
+ assert(IS_PAGE_ALIGNED(ro_limit));
+ assert(IS_PAGE_ALIGNED(coh_start));
+ assert(IS_PAGE_ALIGNED(coh_limit));
+
fill_xlation_tables(mem_layout,
ro_start,
ro_limit,
diff --git a/plat/fvp/aarch64/fvp_helpers.S b/plat/fvp/aarch64/fvp_helpers.S
index 250149b..7a893d0 100644
--- a/plat/fvp/aarch64/fvp_helpers.S
+++ b/plat/fvp/aarch64/fvp_helpers.S
@@ -33,7 +33,7 @@
.globl plat_report_exception
- .section platform_code, "ax"
+ .section .text, "ax"
/* ---------------------------------------------
* void plat_report_exception(unsigned int type)