path: root/docs
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authorAchin Gupta <achin.gupta@arm.com>2013-11-25 18:45:02 +0000
committerDan Handley <dan.handley@arm.com>2013-12-05 12:28:50 +0000
commitc8afc789196cdd568e29aa1e54cb5d24be5adf70 (patch)
treec29ea6f222a2f76cda944ed976b6e734e393732e /docs
parent994dfceb449a7b2fe34a1febd765cc5291172b39 (diff)
psci: fix error due to a non zero context id
In the previous psci implementation, the psci_afflvl_power_on_finish() function would run into an error condition if the value of the context id parameter in the cpu_on and cpu_suspend psci calls was != 0. The parameter was being restored as the return value of the affinity level 0 finisher function. A non zero context id would be treated as an error condition. This would prevent successful wake up of the cpu from a power down state. Also, the contents of the general purpose registers were not being cleared upon return to the non-secure world after a cpu power up. This could potentially allow the non-secure world to view secure data. This patch ensures that all general purpose registers are set to ~0 prior to the final eret that drops the execution to the non-secure world. The context id is used to initialize the general purpose register x0 prior to re-entry into the non-secure world and is no longer restored as a function return value. A platform helper (platform_get_stack()) has been introduced to facilitate this change. Change-Id: I2454911ffd75705d6aa8609a5d250d9b26fa097c
Diffstat (limited to 'docs')
2 files changed, 21 insertions, 2 deletions
diff --git a/docs/change-log.md b/docs/change-log.md
index 73d7e7a..8be7a51 100644
--- a/docs/change-log.md
+++ b/docs/change-log.md
@@ -52,6 +52,10 @@ Detailed changes since last release
* Definitions of some constants related to the PSCI api calls AFFINITY_INFO
and CPU_SUSPEND have been corrected.
+* A bug which triggered an error condition in the code executed after a cpu
+ is powered on, if a non zero context id parameter was passed in the PSCI
+ CPU_ON and CPU_SUSPEND api calls has been corrected.
ARM Trusted Firmware - version 0.2
diff --git a/docs/porting-guide.md b/docs/porting-guide.md
index 0b07111..c0e6ace 100644
--- a/docs/porting-guide.md
+++ b/docs/porting-guide.md
@@ -188,8 +188,9 @@ the implementer chooses. In the ARM FVP port, they are implemented in
bytes) of the largest cache line amongst all caches implemented in the
system. A pointer to this memory should be exported with the name
`platform_normal_stacks`. This pointer is used by the common platform helper
- function `platform_set_stack()` to allocate a stack to each CPU in the
- platform (see [../plat/common/aarch64/platform_helpers.S]).
+ functions `platform_set_stack()` (to allocate a stack for each CPU in the
+ platform) & `platform_get_stack()` (to return the base address of that
+ stack) (see [../plat/common/aarch64/platform_helpers.S]).
2.2 Common optional modifications
@@ -262,6 +263,20 @@ The size of the stack allocated to each CPU is specified by the platform defined
+### Function : platform_get_stack()
+ Argument : unsigned long
+ Return : unsigned long
+This function uses the `platform_normal_stacks` pointer variable to return the
+base address of the stack memory reserved for a CPU. Further details are given
+in the description of the `platform_normal_stacks` variable below. A CPU is
+identified by its `MPIDR`, which is passed as the argument.
+The size of the stack allocated to each CPU is specified by the platform defined
### Function : plat_report_exception()
Argument : unsigned int