|author||Sandrine Bailleux <email@example.com>||2014-03-31 11:25:18 +0100|
|committer||Sandrine Bailleux <firstname.lastname@example.org>||2014-04-08 15:22:56 +0100|
Define frequency of system counter in platform code
BL3-1 architecture setup code programs the system counter frequency into the CNTFRQ_EL0 register. This frequency is defined by the platform, though. This patch introduces a new platform hook that the architecture setup code can call to retrieve this information. In the ARM FVP port, this returns the first entry of the frequency modes table from the memory mapped generic timer. All system counter setup code has been removed from BL1 as some platforms may not have initialized the system counters at this stage. The platform specific settings done exclusively in BL1 have been moved to BL3-1. In the ARM FVP port, this consists in enabling and initializing the System level generic timer. Also, the frequency change request in the counter control register has been set to 0 to make it explicit it's using the base frequency. The CNTCR_FCREQ() macro has been fixed in this context to give an entry number rather than a bitmask. In future, when support for firmware update is implemented, there is a case where BL1 platform specific code will need to program the counter frequency. This should be implemented at that time. This patch also updates the relevant documentation. It properly fixes ARM-software/tf-issues#24 Change-Id: If95639b279f75d66ac0576c48a6614b5ccb0e84b
Diffstat (limited to 'docs')
2 files changed, 12 insertions, 12 deletions
diff --git a/docs/firmware-design.md b/docs/firmware-design.md
index 2bf57ca..8c635a9 100644
@@ -151,13 +151,6 @@ BL1 performs minimal architectural initialization as follows.
and Advanced SIMD execution are configured to not trap to EL3 by
clearing the `CPTR_EL3.TFP` bit.
- - `CNTFRQ_EL0`. The `CNTFRQ_EL0` register is programmed with the base
- frequency of the system counter, which is retrieved from the first entry
- in the frequency modes table.
- - Generic Timer. The system level implementation of the generic timer is
- enabled through the memory mapped interface.
#### Platform initialization
BL1 enables issuing of snoop and DVM (Distributed Virtual Memory) requests from
@@ -291,7 +284,8 @@ exception is raised. They implement more elaborate support for handling SMCs
since this is the only mechanism to access the runtime services implemented by
BL3-1 (PSCI for example). BL3-1 checks each SMC for validity as specified by
the [SMC calling convention PDD][SMCCC] before passing control to the required
-SMC handler routine.
+SMC handler routine. BL3-1 programs the `CNTFRQ_EL0` register with the clock
+frequency of the system counter, which is provided by the platform.
#### Platform initialization
@@ -299,7 +293,8 @@ BL3-1 performs detailed platform initialization, which enables normal world
software to function correctly. It also retrieves entrypoint information for
the BL3-3 image loaded by BL2 from the platform defined memory address populated
by BL2. BL3-1 also initializes UART0 (PL011 console), which enables
-access to the `printf` family of functions in BL3-1
+access to the `printf` family of functions in BL3-1. It enables the system
+level implementation of the generic timer through the memory mapped interface.
* GICv2 initialization:
diff --git a/docs/porting-guide.md b/docs/porting-guide.md
index 56467fb..5dca6fd 100644
@@ -208,6 +208,13 @@ the implementer chooses. In the ARM FVP port, they are implemented in
platform) & `platform_get_stack()` (to return the base address of that
stack) (see [../plat/common/aarch64/platform_helpers.S]).
+* **Function : uint64_t plat_get_syscnt_freq(void)**
+ This function is used by the architecture setup code to retrieve the
+ counter frequency for the CPU's generic timer. This value will be
+ programmed into the `CNTFRQ_EL0` register.
+ In the ARM FVP port, it returns the base frequency of the system counter,
+ which is retrieved from the first entry in the frequency modes table.
2.2 Common optional modifications
@@ -446,9 +453,6 @@ This function executes with the MMU and data caches enabled. It is responsible
for performing any remaining platform-specific setup that can occur after the
MMU and data cache have been enabled.
-In the ARM FVP port, it zeros out the ZI section and enables the system level
-implementation of the generic timer counter.
This function is also responsible for initializing the storage abstraction layer
which is used to load further bootloader images.
@@ -771,6 +775,7 @@ BL3-1 runtime services and normal world software can function correctly.
The ARM FVP port does the following:
* Initializes the generic interrupt controller.
* Configures the CLCD controller.
+* Enables system-level implementation of the generic timer counter.
* Grants access to the system counter timer module
* Initializes the FVP power controller device
* Detects the system topology.