path: root/docs
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authorAndrew Thoelke <andrew.thoelke@arm.com>2014-05-09 15:36:13 +0100
committerAndrew Thoelke <andrew.thoelke@arm.com>2014-05-12 14:21:53 +0100
commit84dbf6ffbf70ac41493471aa0a9b04d287a5b495 (patch)
treeb48ac36344b5a803c23861d8372a23fe797926dc /docs
parent60bc4bbd0bf705f30327e3c37973bcf1e1851110 (diff)
Fixes for TZC configuration on FVP
The TZC configuration on FVP was incorrectly allowing both secure and non-secure accesses to the DRAM, which can cause aliasing problems for software. It was also not enabling virtio access on some models. This patch fixes both of those issues. The patch also enabless non-secure access to the DDR RAM for all devices with defined IDs. The third region of DDR RAM has been removed from the configuration as this is not used in any of the FVP models. Fixes ARM-software/tf-issues#150 Fixes ARM-software/tf-issues#151 Change-Id: I60ad5daaf55e14f178affb8afd95d17e7537abd7
Diffstat (limited to 'docs')
1 files changed, 4 insertions, 2 deletions
diff --git a/docs/porting-guide.md b/docs/porting-guide.md
index 8a024d8..e967b0e 100644
--- a/docs/porting-guide.md
+++ b/docs/porting-guide.md
@@ -631,8 +631,10 @@ this function. This information is accessible in the `bl33_meminfo` field in
the `bl31_args` structure pointed to by `bl2_to_bl31_args`.
Platform security components are configured if required. For the Base FVP the
-TZC-400 TrustZone controller is configured to grant secure and non-secure access
-to DRAM.
+TZC-400 TrustZone controller is configured to only grant non-secure access
+to DRAM. This avoids aliasing between secure and non-secure accesses in the
+TLB and cache - secure execution states can use the NS attributes in the
+MMU translation tables to access the DRAM.
This function is also responsible for initializing the storage abstraction layer
which is used to load further bootloader images.