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authorSandrine Bailleux <sandrine.bailleux@arm.com>2013-11-18 17:26:59 +0000
committerDan Handley <dan.handley@arm.com>2013-11-27 15:31:06 +0000
commit3738274dc1b40ad846d41d7bfd6a597bcfba9e70 (patch)
tree136c4d81d7b4f285ee37f1fdf674df5332a238d4 /docs/user-guide.md
parent204aa03da7d8a34d5e06fba3ccc9e565ed01d305 (diff)
downloadarm-trusted-firmware-3738274dc1b40ad846d41d7bfd6a597bcfba9e70.tar.gz
Unmask SError and Debug exceptions.
Any asynchronous exception caused by the firmware should be handled in the firmware itself. For this reason, unmask SError exceptions (and Debug ones as well) on all boot paths. Also route external abort and SError interrupts to EL3, otherwise they will target EL1. Change-Id: I9c191d2d0dcfef85f265641c8460dfbb4d112092
Diffstat (limited to 'docs/user-guide.md')
-rw-r--r--docs/user-guide.md4
1 files changed, 3 insertions, 1 deletions
diff --git a/docs/user-guide.md b/docs/user-guide.md
index debda44..45e850b 100644
--- a/docs/user-guide.md
+++ b/docs/user-guide.md
@@ -661,7 +661,9 @@ BL1 performs minimal architectural initialization as follows.
- `SCR`. Use of the HVC instruction from EL1 is enabled by setting the
`SCR.HCE` bit. FIQ exceptions are configured to be taken in EL3 by
setting the `SCR.FIQ` bit. The register width of the next lower
- exception level is set to AArch64 by setting the `SCR.RW` bit.
+ exception level is set to AArch64 by setting the `SCR.RW` bit. External
+ Aborts and SError Interrupts are configured to be taken in EL3 by
+ setting the `SCR.EA` bit.
- `CPTR_EL3`. Accesses to the `CPACR` from EL1 or EL2, or the `CPTR_EL2`
from EL2 are configured to not trap to EL3 by clearing the