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authorSandrine Bailleux <sandrine.bailleux@arm.com>2014-05-21 17:08:26 +0100
committerSandrine Bailleux <sandrine.bailleux@arm.com>2014-05-23 11:05:44 +0100
commit638363eb5f548773c4eb7c9c0d21b87576064f28 (patch)
tree62b06ba6fa04810783a5c2170a945e98755644fc /docs/porting-guide.md
parenta37255a205fa004bfc075aca81cef45b99dc30cb (diff)
downloadarm-trusted-firmware-638363eb5f548773c4eb7c9c0d21b87576064f28.tar.gz
doc: Update information about the memory layout
Rework the "Memory layout on FVP platforms" section in the Firmware Design document. Add information about where the TSP image fits in the memory layout when present. Add documentation for the base addresses of each bootloader image in the porting guide. Change-Id: I4afb2605e008a1cb28c44a697804f2cb6bb4c9aa
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diff --git a/docs/porting-guide.md b/docs/porting-guide.md
index c66279c..37c2bf9 100644
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+++ b/docs/porting-guide.md
@@ -180,16 +180,44 @@ constants defined. In the ARM FVP port, this file is found in
Defines the base address of the `CNTCTLBase` frame of the memory mapped
counter and timer in the system level implementation of the generic timer.
+* **#define : BL1_RO_BASE**
+
+ Defines the base address in secure ROM where BL1 originally lives. Must be
+ aligned on a page-size boundary.
+
+* **#define : BL1_RO_LIMIT**
+
+ Defines the maximum address in secure ROM that BL1's actual content (i.e.
+ excluding any data section allocated at runtime) can occupy.
+
+* **#define : BL1_RW_BASE**
+
+ Defines the base address in secure RAM where BL1's read-write data will live
+ at runtime. Must be aligned on a page-size boundary.
+
+* **#define : BL1_RW_LIMIT**
+
+ Defines the maximum address in secure RAM that BL1's read-write data can
+ occupy at runtime.
+
* **#define : BL2_BASE**
Defines the base address in secure RAM where BL1 loads the BL2 binary image.
Must be aligned on a page-size boundary.
+* **#define : BL2_LIMIT**
+
+ Defines the maximum address in secure RAM that the BL2 image can occupy.
+
* **#define : BL31_BASE**
Defines the base address in secure RAM where BL2 loads the BL3-1 binary
image. Must be aligned on a page-size boundary.
+* **#define : BL31_LIMIT**
+
+ Defines the maximum address in secure RAM that the BL3-1 image can occupy.
+
* **#define : NS_IMAGE_OFFSET**
Defines the base address in non-secure DRAM where BL2 loads the BL3-3 binary