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authorSandrine Bailleux <sandrine.bailleux@arm.com>2013-10-25 15:33:39 +0100
committerDan Handley <dan.handley@arm.com>2013-11-27 15:31:06 +0000
commit27866d84283580be3d41155008d47622e87667da (patch)
treee7e642ec6a62668073c96bcfb39e6ff1739b81a1 /arch
parentc10bd2ce69e54a8c71fa773810e130fc465c03ac (diff)
downloadarm-trusted-firmware-27866d84283580be3d41155008d47622e87667da.tar.gz
Fix inlining of GIC helper functions
Change-Id: I27aad560a5da21c0439f3ccc9dc07b026e7c6022
Diffstat (limited to 'arch')
-rw-r--r--arch/system/gic/gic.h27
-rw-r--r--arch/system/gic/gic_v2.c141
-rw-r--r--arch/system/gic/gic_v2.h156
-rw-r--r--arch/system/gic/gic_v3.h (renamed from arch/system/gic/gic_v3.c)13
4 files changed, 172 insertions, 165 deletions
diff --git a/arch/system/gic/gic.h b/arch/system/gic/gic.h
index 91ada03..f38f42b 100644
--- a/arch/system/gic/gic.h
+++ b/arch/system/gic/gic.h
@@ -141,11 +141,13 @@
#ifndef __ASSEMBLY__
+#include <gic_v2.h>
+#include <gic_v3.h>
+
/*******************************************************************************
* Function prototypes
******************************************************************************/
-extern inline unsigned int gicd_read_typer(unsigned int);
-extern inline unsigned int gicd_read_ctlr(unsigned int);
+
extern unsigned int gicd_read_igroupr(unsigned int, unsigned int);
extern unsigned int gicd_read_isenabler(unsigned int, unsigned int);
extern unsigned int gicd_read_icenabler(unsigned int, unsigned int);
@@ -156,10 +158,8 @@ extern unsigned int gicd_read_icactiver(unsigned int, unsigned int);
extern unsigned int gicd_read_ipriorityr(unsigned int, unsigned int);
extern unsigned int gicd_read_itargetsr(unsigned int, unsigned int);
extern unsigned int gicd_read_icfgr(unsigned int, unsigned int);
-extern unsigned int gicd_read_sgir(unsigned int);
extern unsigned int gicd_read_cpendsgir(unsigned int, unsigned int);
extern unsigned int gicd_read_spendsgir(unsigned int, unsigned int);
-extern inline void gicd_write_ctlr(unsigned int, unsigned int);
extern void gicd_write_igroupr(unsigned int, unsigned int, unsigned int);
extern void gicd_write_isenabler(unsigned int, unsigned int, unsigned int);
extern void gicd_write_icenabler(unsigned int, unsigned int, unsigned int);
@@ -170,7 +170,6 @@ extern void gicd_write_icactiver(unsigned int, unsigned int, unsigned int);
extern void gicd_write_ipriorityr(unsigned int, unsigned int, unsigned int);
extern void gicd_write_itargetsr(unsigned int, unsigned int, unsigned int);
extern void gicd_write_icfgr(unsigned int, unsigned int, unsigned int);
-extern void gicd_write_sgir(unsigned int, unsigned int);
extern void gicd_write_cpendsgir(unsigned int, unsigned int, unsigned int);
extern void gicd_write_spendsgir(unsigned int, unsigned int, unsigned int);
extern unsigned int gicd_get_igroupr(unsigned int, unsigned int);
@@ -184,25 +183,9 @@ extern void gicd_set_isactiver(unsigned int, unsigned int);
extern void gicd_set_icactiver(unsigned int, unsigned int);
extern void gicd_set_ipriorityr(unsigned int, unsigned int, unsigned int);
extern void gicd_set_itargetsr(unsigned int, unsigned int, unsigned int);
-extern inline unsigned int gicc_read_ctlr(unsigned int);
-extern inline unsigned int gicc_read_pmr(unsigned int);
-extern inline unsigned int gicc_read_BPR(unsigned int);
-extern inline unsigned int gicc_read_IAR(unsigned int);
-extern inline unsigned int gicc_read_EOIR(unsigned int);
-extern inline unsigned int gicc_read_hppir(unsigned int);
-extern inline unsigned int gicc_read_iidr(unsigned int);
-extern inline unsigned int gicc_read_dir(unsigned int);
-extern inline void gicc_write_ctlr(unsigned int, unsigned int);
-extern inline void gicc_write_pmr(unsigned int, unsigned int);
-extern inline void gicc_write_BPR(unsigned int, unsigned int);
-extern inline void gicc_write_IAR(unsigned int, unsigned int);
-extern inline void gicc_write_EOIR(unsigned int, unsigned int);
-extern inline void gicc_write_hppir(unsigned int, unsigned int);
-extern inline void gicc_write_dir(unsigned int, unsigned int);
/* GICv3 functions */
-extern inline unsigned int gicr_read_waker(unsigned int);
-extern inline void gicr_write_waker(unsigned int, unsigned int);
+
extern unsigned int read_icc_sre_el1(void);
extern unsigned int read_icc_sre_el2(void);
extern unsigned int read_icc_sre_el3(void);
diff --git a/arch/system/gic/gic_v2.c b/arch/system/gic/gic_v2.c
index 4b3d0c5..f8de290 100644
--- a/arch/system/gic/gic_v2.c
+++ b/arch/system/gic/gic_v2.c
@@ -32,17 +32,8 @@
#include <mmio.h>
/*******************************************************************************
- * GIC Distributor interface accessesors for reading entire registers
+ * GIC Distributor interface accessors for reading entire registers
******************************************************************************/
-inline unsigned int gicd_read_ctlr(unsigned int base)
-{
- return mmio_read_32(base + GICD_CTLR);
-}
-
-inline unsigned int gicd_read_typer(unsigned int base)
-{
- return mmio_read_32(base + GICD_TYPER);
-}
unsigned int gicd_read_igroupr(unsigned int base, unsigned int id)
{
@@ -104,11 +95,6 @@ unsigned int gicd_read_icfgr(unsigned int base, unsigned int id)
return mmio_read_32(base + GICD_ICFGR + (n << 2));
}
-unsigned int gicd_read_sgir(unsigned int base)
-{
- return mmio_read_32(base + GICD_SGIR);
-}
-
unsigned int gicd_read_cpendsgir(unsigned int base, unsigned int id)
{
unsigned n = id >> CPENDSGIR_SHIFT;
@@ -122,106 +108,83 @@ unsigned int gicd_read_spendsgir(unsigned int base, unsigned int id)
}
/*******************************************************************************
- * GIC Distributor interface accessesors for writing entire registers
+ * GIC Distributor interface accessors for writing entire registers
******************************************************************************/
-inline void gicd_write_ctlr(unsigned int base, unsigned int val)
-{
- mmio_write_32(base + GICD_CTLR, val);
- return;
-}
void gicd_write_igroupr(unsigned int base, unsigned int id, unsigned int val)
{
unsigned n = id >> IGROUPR_SHIFT;
mmio_write_32(base + GICD_IGROUPR + (n << 2), val);
- return;
}
void gicd_write_isenabler(unsigned int base, unsigned int id, unsigned int val)
{
unsigned n = id >> ISENABLER_SHIFT;
mmio_write_32(base + GICD_ISENABLER + (n << 2), val);
- return;
}
void gicd_write_icenabler(unsigned int base, unsigned int id, unsigned int val)
{
unsigned n = id >> ICENABLER_SHIFT;
mmio_write_32(base + GICD_ICENABLER + (n << 2), val);
- return;
}
void gicd_write_ispendr(unsigned int base, unsigned int id, unsigned int val)
{
unsigned n = id >> ISPENDR_SHIFT;
mmio_write_32(base + GICD_ISPENDR + (n << 2), val);
- return;
}
void gicd_write_icpendr(unsigned int base, unsigned int id, unsigned int val)
{
unsigned n = id >> ICPENDR_SHIFT;
mmio_write_32(base + GICD_ICPENDR + (n << 2), val);
- return;
}
void gicd_write_isactiver(unsigned int base, unsigned int id, unsigned int val)
{
unsigned n = id >> ISACTIVER_SHIFT;
mmio_write_32(base + GICD_ISACTIVER + (n << 2), val);
- return;
}
void gicd_write_icactiver(unsigned int base, unsigned int id, unsigned int val)
{
unsigned n = id >> ICACTIVER_SHIFT;
mmio_write_32(base + GICD_ICACTIVER + (n << 2), val);
- return;
}
void gicd_write_ipriorityr(unsigned int base, unsigned int id, unsigned int val)
{
unsigned n = id >> IPRIORITYR_SHIFT;
mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val);
- return;
}
void gicd_write_itargetsr(unsigned int base, unsigned int id, unsigned int val)
{
unsigned n = id >> ITARGETSR_SHIFT;
mmio_write_32(base + GICD_ITARGETSR + (n << 2), val);
- return;
}
void gicd_write_icfgr(unsigned int base, unsigned int id, unsigned int val)
{
unsigned n = id >> ICFGR_SHIFT;
mmio_write_32(base + GICD_ICFGR + (n << 2), val);
- return;
-}
-
-void gicd_write_sgir(unsigned int base, unsigned int val)
-{
- mmio_write_32(base + GICD_SGIR, val);
- return;
}
void gicd_write_cpendsgir(unsigned int base, unsigned int id, unsigned int val)
{
unsigned n = id >> CPENDSGIR_SHIFT;
mmio_write_32(base + GICD_CPENDSGIR + (n << 2), val);
- return;
}
void gicd_write_spendsgir(unsigned int base, unsigned int id, unsigned int val)
{
unsigned n = id >> SPENDSGIR_SHIFT;
mmio_write_32(base + GICD_SPENDSGIR + (n << 2), val);
- return;
}
/*******************************************************************************
- * GIC Distributor interface accessesors for individual interrupt manipulation
+ * GIC Distributor interface accessors for individual interrupt manipulation
******************************************************************************/
unsigned int gicd_get_igroupr(unsigned int base, unsigned int id)
{
@@ -237,7 +200,6 @@ void gicd_set_igroupr(unsigned int base, unsigned int id)
unsigned int reg_val = gicd_read_igroupr(base, id);
gicd_write_igroupr(base, id, reg_val | (1 << bit_num));
- return;
}
void gicd_clr_igroupr(unsigned int base, unsigned int id)
@@ -246,7 +208,6 @@ void gicd_clr_igroupr(unsigned int base, unsigned int id)
unsigned int reg_val = gicd_read_igroupr(base, id);
gicd_write_igroupr(base, id, reg_val & ~(1 << bit_num));
- return;
}
void gicd_set_isenabler(unsigned int base, unsigned int id)
@@ -255,7 +216,6 @@ void gicd_set_isenabler(unsigned int base, unsigned int id)
unsigned int reg_val = gicd_read_isenabler(base, id);
gicd_write_isenabler(base, id, reg_val | (1 << bit_num));
- return;
}
void gicd_set_icenabler(unsigned int base, unsigned int id)
@@ -264,7 +224,6 @@ void gicd_set_icenabler(unsigned int base, unsigned int id)
unsigned int reg_val = gicd_read_icenabler(base, id);
gicd_write_icenabler(base, id, reg_val & ~(1 << bit_num));
- return;
}
void gicd_set_ispendr(unsigned int base, unsigned int id)
@@ -273,7 +232,6 @@ void gicd_set_ispendr(unsigned int base, unsigned int id)
unsigned int reg_val = gicd_read_ispendr(base, id);
gicd_write_ispendr(base, id, reg_val | (1 << bit_num));
- return;
}
void gicd_set_icpendr(unsigned int base, unsigned int id)
@@ -282,7 +240,6 @@ void gicd_set_icpendr(unsigned int base, unsigned int id)
unsigned int reg_val = gicd_read_icpendr(base, id);
gicd_write_icpendr(base, id, reg_val & ~(1 << bit_num));
- return;
}
void gicd_set_isactiver(unsigned int base, unsigned int id)
@@ -291,7 +248,6 @@ void gicd_set_isactiver(unsigned int base, unsigned int id)
unsigned int reg_val = gicd_read_isactiver(base, id);
gicd_write_isactiver(base, id, reg_val | (1 << bit_num));
- return;
}
void gicd_set_icactiver(unsigned int base, unsigned int id)
@@ -300,7 +256,6 @@ void gicd_set_icactiver(unsigned int base, unsigned int id)
unsigned int reg_val = gicd_read_icactiver(base, id);
gicd_write_icactiver(base, id, reg_val & ~(1 << bit_num));
- return;
}
/*
@@ -323,7 +278,6 @@ void gicd_set_ipriorityr(unsigned int base, unsigned int id, unsigned int pri)
pri &= ~(1 << 7);
gicd_write_icactiver(base, id, reg_val & ~(pri << (byte_off << 3)));
- return;
}
void gicd_set_itargetsr(unsigned int base, unsigned int id, unsigned int iface)
@@ -333,94 +287,5 @@ void gicd_set_itargetsr(unsigned int base, unsigned int id, unsigned int iface)
gicd_write_itargetsr(base, id, reg_val |
(1 << iface) << (byte_off << 3));
- return;
-}
-
-/*******************************************************************************
- * GIC CPU interface accessesors for reading entire registers
- ******************************************************************************/
-inline unsigned int gicc_read_ctlr(unsigned int base)
-{
- return mmio_read_32(base + GICC_CTLR);
-}
-
-inline unsigned int gicc_read_pmr(unsigned int base)
-{
- return mmio_read_32(base + GICC_PMR);
-}
-
-inline unsigned int gicc_read_BPR(unsigned int base)
-{
- return mmio_read_32(base + GICC_BPR);
-}
-
-inline unsigned int gicc_read_IAR(unsigned int base)
-{
- return mmio_read_32(base + GICC_IAR);
-}
-
-inline unsigned int gicc_read_EOIR(unsigned int base)
-{
- return mmio_read_32(base + GICC_EOIR);
-}
-
-inline unsigned int gicc_read_hppir(unsigned int base)
-{
- return mmio_read_32(base + GICC_HPPIR);
-}
-
-inline unsigned int gicc_read_dir(unsigned int base)
-{
- return mmio_read_32(base + GICC_DIR);
-}
-
-inline unsigned int gicc_read_iidr(unsigned int base)
-{
- return mmio_read_32(base + GICC_IIDR);
-}
-
-/*******************************************************************************
- * GIC CPU interface accessesors for writing entire registers
- ******************************************************************************/
-inline void gicc_write_ctlr(unsigned int base, unsigned int val)
-{
- mmio_write_32(base + GICC_CTLR, val);
- return;
-}
-
-inline void gicc_write_pmr(unsigned int base, unsigned int val)
-{
- mmio_write_32(base + GICC_PMR, val);
- return;
-}
-
-inline void gicc_write_BPR(unsigned int base, unsigned int val)
-{
- mmio_write_32(base + GICC_BPR, val);
- return;
-}
-
-inline void gicc_write_IAR(unsigned int base, unsigned int val)
-{
- mmio_write_32(base + GICC_IAR, val);
- return;
-}
-
-inline void gicc_write_EOIR(unsigned int base, unsigned int val)
-{
- mmio_write_32(base + GICC_EOIR, val);
- return;
-}
-
-inline void gicc_write_hppir(unsigned int base, unsigned int val)
-{
- mmio_write_32(base + GICC_HPPIR, val);
- return;
-}
-
-inline void gicc_write_dir(unsigned int base, unsigned int val)
-{
- mmio_write_32(base + GICC_DIR, val);
- return;
}
diff --git a/arch/system/gic/gic_v2.h b/arch/system/gic/gic_v2.h
new file mode 100644
index 0000000..c944df6
--- /dev/null
+++ b/arch/system/gic/gic_v2.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2013, ARM Limited. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __GIC_V2_H__
+#define __GIC_V2_H__
+
+#include <mmio.h>
+
+/*******************************************************************************
+ * GIC Distributor interface accessors for reading entire registers
+ ******************************************************************************/
+
+static inline unsigned int gicd_read_ctlr(unsigned int base)
+{
+ return mmio_read_32(base + GICD_CTLR);
+}
+
+static inline unsigned int gicd_read_typer(unsigned int base)
+{
+ return mmio_read_32(base + GICD_TYPER);
+}
+
+static inline unsigned int gicd_read_sgir(unsigned int base)
+{
+ return mmio_read_32(base + GICD_SGIR);
+}
+
+
+/*******************************************************************************
+ * GIC Distributor interface accessors for writing entire registers
+ ******************************************************************************/
+
+static inline void gicd_write_ctlr(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + GICD_CTLR, val);
+}
+
+static inline void gicd_write_sgir(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + GICD_SGIR, val);
+}
+
+
+/*******************************************************************************
+ * GIC CPU interface accessors for reading entire registers
+ ******************************************************************************/
+
+static inline unsigned int gicc_read_ctlr(unsigned int base)
+{
+ return mmio_read_32(base + GICC_CTLR);
+}
+
+static inline unsigned int gicc_read_pmr(unsigned int base)
+{
+ return mmio_read_32(base + GICC_PMR);
+}
+
+static inline unsigned int gicc_read_BPR(unsigned int base)
+{
+ return mmio_read_32(base + GICC_BPR);
+}
+
+static inline unsigned int gicc_read_IAR(unsigned int base)
+{
+ return mmio_read_32(base + GICC_IAR);
+}
+
+static inline unsigned int gicc_read_EOIR(unsigned int base)
+{
+ return mmio_read_32(base + GICC_EOIR);
+}
+
+static inline unsigned int gicc_read_hppir(unsigned int base)
+{
+ return mmio_read_32(base + GICC_HPPIR);
+}
+
+static inline unsigned int gicc_read_dir(unsigned int base)
+{
+ return mmio_read_32(base + GICC_DIR);
+}
+
+static inline unsigned int gicc_read_iidr(unsigned int base)
+{
+ return mmio_read_32(base + GICC_IIDR);
+}
+
+
+/*******************************************************************************
+ * GIC CPU interface accessors for writing entire registers
+ ******************************************************************************/
+
+static inline void gicc_write_ctlr(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + GICC_CTLR, val);
+}
+
+static inline void gicc_write_pmr(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + GICC_PMR, val);
+}
+
+static inline void gicc_write_BPR(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + GICC_BPR, val);
+}
+
+
+static inline void gicc_write_IAR(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + GICC_IAR, val);
+}
+
+static inline void gicc_write_EOIR(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + GICC_EOIR, val);
+}
+
+static inline void gicc_write_hppir(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + GICC_HPPIR, val);
+}
+
+static inline void gicc_write_dir(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + GICC_DIR, val);
+}
+
+#endif /* __GIC_V2_H__ */
diff --git a/arch/system/gic/gic_v3.c b/arch/system/gic/gic_v3.h
index 7806a0d..a4fe2ce 100644
--- a/arch/system/gic/gic_v3.c
+++ b/arch/system/gic/gic_v3.h
@@ -28,19 +28,22 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include <gic.h>
+#ifndef __GIC_V3_H__
+#define __GIC_V3_H__
+
#include <mmio.h>
/*******************************************************************************
- * GIC Redistributor interface accessesors
+ * GIC Redistributor interface accessors
******************************************************************************/
-inline unsigned int gicr_read_waker(unsigned int base)
+static inline unsigned int gicr_read_waker(unsigned int base)
{
return mmio_read_32(base + GICR_WAKER);
}
-inline void gicr_write_waker(unsigned int base, unsigned int val)
+static inline void gicr_write_waker(unsigned int base, unsigned int val)
{
mmio_write_32(base + GICR_WAKER, val);
- return;
}
+
+#endif /* __GIC_V3_H__ */