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authorSandrine Bailleux <sandrine.bailleux@arm.com>2014-05-20 17:28:25 +0100
committerSandrine Bailleux <sandrine.bailleux@arm.com>2014-05-22 17:30:58 +0100
commit53514b29095a41e05a81289e7e1e08f8feeba945 (patch)
treeb1008a3b378d4d1b451e34903bb68d4edb480fd7
parent2467f70fde43fefa38564d871e78f1f882dfe540 (diff)
downloadarm-trusted-firmware-53514b29095a41e05a81289e7e1e08f8feeba945.tar.gz
fvp: Move TSP from Secure DRAM to Secure SRAM
The TSP used to execute from secure DRAM on the FVPs because there was not enough space in Trusted SRAM to fit it in. Thanks to recent RAM usage enhancements being implemented, we have made enough savings for the TSP to execute in SRAM. However, there is no contiguous free chunk of SRAM big enough to hold the TSP. Therefore, the different bootloader images need to be moved around to reduce memory fragmentation. This patch keeps the overall memory layout (i.e. keeping BL1 R/W at the bottom, BL2 at the top and BL3-1 in between) but moves the base addresses of all the bootloader images in such a way that: - memory fragmentation is reduced enough to fit BL3-2 in; - new base addresses are suitable for release builds as well as debug ones; - each image has a few extra kilobytes for future growth. BL3-1 and BL3-2 are the images which received the biggest slice of the cake since they will most probably grow the most. A few useful numbers for reference (valid at the time of this patch): |-----------------------|------------------------------- | image size (debug) | extra space for the future --------|-----------------------|------------------------------- BL1 R/W | 20 KB | 4 KB BL2 | 44 KB | 4 KB BL3-1 | 108 KB | 12 KB BL3-2 | 56 KB | 8 KB --------|-----------------------|------------------------------- Total | 228 KB | 28 KB = 256 KB --------|-----------------------|------------------------------- Although on FVPs the TSP now executes from Trusted SRAM by default, this patch keeps the option to execute it from Trusted DRAM. This is controlled by the build configuration 'TSP_RAM_LOCATION'. Fixes ARM-Software/tf-issues#81 Change-Id: Ifb9ef2befa9a2d5ac0813f7f79834df7af992b94
-rw-r--r--bl32/tsp/tsp.ld.S2
-rw-r--r--plat/fvp/bl2_plat_setup.c4
-rw-r--r--plat/fvp/platform.h27
-rw-r--r--plat/fvp/platform.mk15
4 files changed, 39 insertions, 9 deletions
diff --git a/bl32/tsp/tsp.ld.S b/bl32/tsp/tsp.ld.S
index 797d8d7..559ae3d 100644
--- a/bl32/tsp/tsp.ld.S
+++ b/bl32/tsp/tsp.ld.S
@@ -113,7 +113,7 @@ SECTIONS
__COHERENT_RAM_END__ = .;
} >RAM
- __BL2_END__ = .;
+ __BL32_END__ = .;
__BSS_SIZE__ = SIZEOF(.bss);
__COHERENT_RAM_UNALIGNED_SIZE__ =
diff --git a/plat/fvp/bl2_plat_setup.c b/plat/fvp/bl2_plat_setup.c
index 672f096..b945db9 100644
--- a/plat/fvp/bl2_plat_setup.c
+++ b/plat/fvp/bl2_plat_setup.c
@@ -98,11 +98,13 @@ bl31_params_t *bl2_plat_get_bl31_params(void)
{
bl2_to_bl31_params_mem_t *bl31_params_mem;
+#if TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
/*
* Ensure that the secure DRAM memory used for passing BL31 arguments
* does not overlap with the BL32_BASE.
*/
assert(BL32_BASE > PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t));
+#endif
/*
* Allocate the memory for all the arguments that needs to
@@ -265,8 +267,6 @@ void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
{
/*
* Populate the extents of memory available for loading BL32.
- * TODO: We are temporarily executing BL2 from TZDRAM;
- * will eventually move to Trusted SRAM
*/
bl32_meminfo->total_base = BL32_BASE;
bl32_meminfo->free_base = BL32_BASE;
diff --git a/plat/fvp/platform.h b/plat/fvp/platform.h
index 07c79d9..981bc98 100644
--- a/plat/fvp/platform.h
+++ b/plat/fvp/platform.h
@@ -238,20 +238,35 @@
/*******************************************************************************
* BL2 specific defines.
******************************************************************************/
-#define BL2_BASE 0x0402D000
+#define BL2_BASE (TZRAM_BASE + TZRAM_SIZE - 0xc000)
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
-#define BL31_BASE 0x0400C000
+#define BL31_BASE (TZRAM_BASE + 0x6000)
/*******************************************************************************
* BL32 specific defines.
******************************************************************************/
-#define TSP_SEC_MEM_BASE TZDRAM_BASE
-#define TSP_SEC_MEM_SIZE TZDRAM_SIZE
-#define BL32_BASE (TZDRAM_BASE + 0x2000)
-#define BL32_LIMIT (TZDRAM_BASE + (1 << 21))
+/*
+ * On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
+ */
+#define TSP_IN_TZRAM 0
+#define TSP_IN_TZDRAM 1
+
+#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM
+# define TSP_SEC_MEM_BASE TZRAM_BASE
+# define TSP_SEC_MEM_SIZE TZRAM_SIZE
+# define BL32_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1c000)
+# define BL32_LIMIT BL2_BASE
+#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
+# define TSP_SEC_MEM_BASE TZDRAM_BASE
+# define TSP_SEC_MEM_SIZE TZDRAM_SIZE
+# define BL32_BASE (TZDRAM_BASE + 0x2000)
+# define BL32_LIMIT (TZDRAM_BASE + (1 << 21))
+#else
+# error "Unsupported TSP_RAM_LOCATION_ID value"
+#endif
/*******************************************************************************
* Platform specific page table and MMU setup constants
diff --git a/plat/fvp/platform.mk b/plat/fvp/platform.mk
index 4de001b..82bafed 100644
--- a/plat/fvp/platform.mk
+++ b/plat/fvp/platform.mk
@@ -28,6 +28,21 @@
# POSSIBILITY OF SUCH DAMAGE.
#
+# On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
+# Trusted SRAM is the default.
+TSP_RAM_LOCATION := tsram
+
+ifeq (${TSP_RAM_LOCATION}, tsram)
+ TSP_RAM_LOCATION_ID := TSP_IN_TZRAM
+else ifeq (${TSP_RAM_LOCATION}, tdram)
+ TSP_RAM_LOCATION_ID := TSP_IN_TZDRAM
+else
+ $(error "Unsupported TSP_RAM_LOCATION value")
+endif
+
+# Process TSP_RAM_LOCATION_ID flag
+$(eval $(call add_define,TSP_RAM_LOCATION_ID))
+
PLAT_INCLUDES := -Iplat/fvp/include/
PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011.c \