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authorSandrine Bailleux <sandrine.bailleux@arm.com>2014-05-22 15:21:35 +0100
committerSandrine Bailleux <sandrine.bailleux@arm.com>2014-05-23 11:05:44 +0100
commit4f59d8359f97e031c212032afeb57124ac4fcd94 (patch)
treeac955313b36992961556715f58f337b6a40e7b76
parentf860e2cf943dc2d240d9a3cd8b37c78192fa9bf9 (diff)
downloadarm-trusted-firmware-4f59d8359f97e031c212032afeb57124ac4fcd94.tar.gz
Make BL1 RO and RW base addresses configurable
BL1 RO and RW base address used to be fixed, respectively to the first address of the Trusted ROM and the first address of the Trusted RAM. Introduce new platform defines to configure the BL1 RO and RW base addresses. Change-Id: If26616513a47798593a4bb845a4b0fb37c867cd6
-rw-r--r--bl1/bl1.ld.S17
-rw-r--r--plat/fvp/platform.h8
2 files changed, 20 insertions, 5 deletions
diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S
index 81c5443..11b9a8f 100644
--- a/bl1/bl1.ld.S
+++ b/bl1/bl1.ld.S
@@ -41,7 +41,11 @@ MEMORY {
SECTIONS
{
- ro : {
+ . = BL1_RO_BASE;
+ ASSERT(. == ALIGN(4096),
+ "BL1_RO_BASE address is not aligned on a page boundary.")
+
+ ro . : {
__RO_START__ = .;
*bl1_entrypoint.o(.text*)
*(.text*)
@@ -52,16 +56,19 @@ SECTIONS
/*
* The .data section gets copied from ROM to RAM at runtime.
- * Its LMA and VMA must be 16-byte aligned.
+ * Its LMA must be 16-byte aligned.
+ * Its VMA must be page-aligned as it marks the first read/write page.
*/
- . = NEXT(16); /* Align LMA */
- .data : ALIGN(16) { /* Align VMA */
+ . = BL1_RW_BASE;
+ ASSERT(. == ALIGN(4096),
+ "BL1_RW_BASE address is not aligned on a page boundary.")
+ .data . : ALIGN(16) {
__DATA_RAM_START__ = .;
*(.data*)
__DATA_RAM_END__ = .;
} >RAM AT>ROM
- stacks (NOLOAD) : {
+ stacks . (NOLOAD) : {
__STACKS_START__ = .;
*(tzfw_normal_stacks)
__STACKS_END__ = .;
diff --git a/plat/fvp/platform.h b/plat/fvp/platform.h
index 981bc98..ff87cf8 100644
--- a/plat/fvp/platform.h
+++ b/plat/fvp/platform.h
@@ -236,6 +236,14 @@
#define PLAT_AFF1_ON 0x3
/*******************************************************************************
+ * BL1 specific defines.
+ * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 base
+ * addresses.
+ ******************************************************************************/
+#define BL1_RO_BASE TZROM_BASE
+#define BL1_RW_BASE TZRAM_BASE
+
+/*******************************************************************************
* BL2 specific defines.
******************************************************************************/
#define BL2_BASE (TZRAM_BASE + TZRAM_SIZE - 0xc000)