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authorFathi Boudra <fathi.boudra@linaro.org>2014-03-11 16:26:02 +0200
committerFathi Boudra <fathi.boudra@linaro.org>2014-03-11 16:26:02 +0200
commita306fde808f3e1bea9a34056aaa64b0869af7244 (patch)
treebc2d78905c2e6619bcdb8a9444cd62691f59166b /meta-linaro-toolchain/recipes-devtools/gcc
parenta801d3c4068f3697850f0573baa759d2beca1d5e (diff)
downloadmeta-linaro-a306fde808f3e1bea9a34056aaa64b0869af7244.tar.gz
gcc-linaro-4.8: update to 2014.03 release
update md5sum/sha256sum sync patches included in oe-core: - 0049-Enable-SPE-AltiVec-generation-on-powepc-linux-target.patch - 0050-PR-target-58595.patch Change-Id: Id043089942c5d9d45fb1b8e1498bcab2a9e2147e Signed-off-by: Fathi Boudra <fathi.boudra@linaro.org>
Diffstat (limited to 'meta-linaro-toolchain/recipes-devtools/gcc')
-rw-r--r--meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.8.inc8
-rw-r--r--meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.8/0049-Enable-SPE-AltiVec-generation-on-powepc-linux-target.patch42
-rw-r--r--meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.8/0050-PR-target-58595.patch101
3 files changed, 148 insertions, 3 deletions
diff --git a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.8.inc b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.8.inc
index 0a0b7f4..b876596 100644
--- a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.8.inc
+++ b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.8.inc
@@ -1,7 +1,7 @@
require recipes-devtools/gcc/gcc-4.8.inc
PV = "linaro-${BASEPV}"
-MMYY = "14.02"
+MMYY = "14.03"
RELEASE = "20${MMYY}"
PR = "r${RELEASE}"
BINV = "4.8.3"
@@ -56,11 +56,13 @@ SRC_URI = "https://releases.linaro.org/${MMYY}/components/toolchain/gcc-linaro/$
file://0046-libatomic-deptracking.patch \
file://0047-repomembug.patch \
file://0048-PR58854_fix_arm_apcs_epilogue.patch;apply=no \
+ file://0049-Enable-SPE-AltiVec-generation-on-powepc-linux-target.patch \
+ file://0050-PR-target-58595.patch \
file://use-lib-for-aarch64.patch \
"
-SRC_URI[md5sum] = "2b3bbea7806931e2048e0fc5983021c8"
-SRC_URI[sha256sum] = "1a6d55292f46c9f717e1e20944ecaa6d8025dd67b1350b7a357b309ae19810e0"
+SRC_URI[md5sum] = "c9023cc7e44eaf68572d6c8549297970"
+SRC_URI[sha256sum] = "0d1511a3c248dcf17d4d2ddbe2a7aa6456aa65dc22dcf3447ff4c457072888dd"
S = "${TMPDIR}/work-shared/gcc-${PV}-${PR}/gcc-${PV}-${RELEASE}"
B = "${WORKDIR}/gcc-${PV}-${RELEASE}/build.${HOST_SYS}.${TARGET_SYS}"
diff --git a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.8/0049-Enable-SPE-AltiVec-generation-on-powepc-linux-target.patch b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.8/0049-Enable-SPE-AltiVec-generation-on-powepc-linux-target.patch
new file mode 100644
index 0000000..b98f8ff
--- /dev/null
+++ b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.8/0049-Enable-SPE-AltiVec-generation-on-powepc-linux-target.patch
@@ -0,0 +1,42 @@
+From 9e0e19eac2562f73858602fe26e2044eb8b20c47 Mon Sep 17 00:00:00 2001
+From: Alexandru-Cezar Sardan <alexandru.sardan@freescale.com>
+Date: Wed, 5 Feb 2014 16:52:31 +0200
+Subject: [PATCH] Enable SPE & AltiVec generation on powepc*linux target
+
+When is configured with --target=powerpc-linux, the resulting GCC will
+not be able to generate code for SPE targets (e500v1/v2).
+GCC configured with --target=powerpc-linuxspe will not be able to
+generate AltiVec instructions (for e6500).
+This patch modifies the configured file such that SPE or AltiVec code
+can be generated when gcc is configured with --target=powerpc-linux.
+The ABI and speciffic instructions can be selected through the
+"-mabi=spe or -mabi=altivec" and the "-mspe or -maltivec" parameters.
+
+Upstream-Status: Inappropriate [configuration]
+
+Signed-off-by: Alexandru-Cezar Sardan <alexandru.sardan@freescale.com>
+---
+ gcc/config.gcc | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/gcc/config.gcc b/gcc/config.gcc
+index cb7a94e..d392c2b 100644
+--- a/gcc/config.gcc
++++ b/gcc/config.gcc
+@@ -2068,7 +2068,12 @@ powerpc-*-rtems*)
+ tmake_file="rs6000/t-fprules rs6000/t-rtems t-rtems rs6000/t-ppccomm"
+ ;;
+ powerpc*-*-linux*)
+- tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h rs6000/sysv4.h"
++ case ${target} in
++ powerpc*-*-linux*spe* | powerpc*-*-linux*altivec*)
++ tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h rs6000/sysv4.h" ;;
++ *)
++ tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h rs6000/sysv4.h rs6000/linuxaltivec.h rs6000/linuxspe.h rs6000/e500.h" ;;
++ esac
+ extra_options="${extra_options} rs6000/sysv4.opt"
+ tmake_file="rs6000/t-fprules rs6000/t-ppcos ${tmake_file} rs6000/t-ppccomm"
+ case ${target} in
+--
+1.7.9.5
+
diff --git a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.8/0050-PR-target-58595.patch b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.8/0050-PR-target-58595.patch
new file mode 100644
index 0000000..62a3994
--- /dev/null
+++ b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.8/0050-PR-target-58595.patch
@@ -0,0 +1,101 @@
+Backport fix for PR target/58595
+
+From: jakub <jakub@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Thu, 6 Mar 2014 12:07:07 +0000
+Subject: [PATCH] PR target/58595 * config/arm/arm.c
+ (arm_tls_symbol_p): Remove. (arm_legitimize_address): Call
+ legitimize_tls_address for any arm_tls_referenced_p expression,
+ handle constant addend. Call it before testing for !TARGET_ARM.
+ (thumb_legitimize_address): Don't handle arm_tls_symbol_p here.
+
+ * gcc.dg/tls/pr58595.c: New test.
+
+
+git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208380 138bc75d-0d04-0410-961f-82ee72b054a4
+
+Index: gcc-4.8.2/gcc/config/arm/arm.c
+===================================================================
+--- gcc-4.8.2.orig/gcc/config/arm/arm.c
++++ gcc-4.8.2/gcc/config/arm/arm.c
+@@ -230,7 +230,6 @@ static tree arm_gimplify_va_arg_expr (tr
+ static void arm_option_override (void);
+ static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
+ static bool arm_cannot_copy_insn_p (rtx);
+-static bool arm_tls_symbol_p (rtx x);
+ static int arm_issue_rate (void);
+ static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
+ static bool arm_output_addr_const_extra (FILE *, rtx);
+@@ -6573,6 +6572,32 @@ legitimize_tls_address (rtx x, rtx reg)
+ rtx
+ arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
+ {
++ if (arm_tls_referenced_p (x))
++ {
++ rtx addend = NULL;
++
++ if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS)
++ {
++ addend = XEXP (XEXP (x, 0), 1);
++ x = XEXP (XEXP (x, 0), 0);
++ }
++
++ if (GET_CODE (x) != SYMBOL_REF)
++ return x;
++
++ gcc_assert (SYMBOL_REF_TLS_MODEL (x) != 0);
++
++ x = legitimize_tls_address (x, NULL_RTX);
++
++ if (addend)
++ {
++ x = gen_rtx_PLUS (SImode, x, addend);
++ orig_x = x;
++ }
++ else
++ return x;
++ }
++
+ if (!TARGET_ARM)
+ {
+ /* TODO: legitimize_address for Thumb2. */
+@@ -6581,9 +6606,6 @@ arm_legitimize_address (rtx x, rtx orig_
+ return thumb_legitimize_address (x, orig_x, mode);
+ }
+
+- if (arm_tls_symbol_p (x))
+- return legitimize_tls_address (x, NULL_RTX);
+-
+ if (GET_CODE (x) == PLUS)
+ {
+ rtx xop0 = XEXP (x, 0);
+@@ -6695,9 +6717,6 @@ arm_legitimize_address (rtx x, rtx orig_
+ rtx
+ thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
+ {
+- if (arm_tls_symbol_p (x))
+- return legitimize_tls_address (x, NULL_RTX);
+-
+ if (GET_CODE (x) == PLUS
+ && CONST_INT_P (XEXP (x, 1))
+ && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
+@@ -6988,20 +7007,6 @@ thumb_legitimize_reload_address (rtx *x_
+
+ /* Test for various thread-local symbols. */
+
+-/* Return TRUE if X is a thread-local symbol. */
+-
+-static bool
+-arm_tls_symbol_p (rtx x)
+-{
+- if (! TARGET_HAVE_TLS)
+- return false;
+-
+- if (GET_CODE (x) != SYMBOL_REF)
+- return false;
+-
+- return SYMBOL_REF_TLS_MODEL (x) != 0;
+-}
+-
+ /* Helper for arm_tls_referenced_p. */
+
+ static int