path: root/virt
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authorSteve Capper <steve.capper@arm.com>2018-01-24 08:27:08 +0000
committerCatalin Marinas <catalin.marinas@arm.com>2018-01-26 18:23:17 +0000
commitec89ab50a03a33a4a648869e868b1964354fb2d1 (patch)
treefca3a39f0042db178584d91eef67f046abe3c2ab /virt
parent0ba2e29c7fc1d58a90fab614d41bf487e28e3840 (diff)
arm64: Fix TTBR + PAN + 52-bit PA logic in cpu_do_switch_mm
In cpu_do_switch_mm(.) with ARM64_SW_TTBR0_PAN=y we apply phys_to_ttbr to a value that already has an ASID inserted into the upper bits. For 52-bit PA configurations this then can give us TTBR0_EL1 registers that cause translation table walks to attempt to access non-zero PA[51:48] spuriously. Ultimately leading to a Synchronous External Abort on level 1 translation. This patch re-arranges the logic in cpu_do_switch_mm(.) such that phys_to_ttbr is called before the ASID is inserted into the TTBR0 value. Fixes: 6b88a32c7af6 ("arm64: kpti: Fix the interaction between ASID switching and software PAN") Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> Tested-by: Kristina Martsenko <kristina.martsenko@arm.com> Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com> Signed-off-by: Steve Capper <steve.capper@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'virt')
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