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authorLinus Torvalds <torvalds@linux-foundation.org>2014-08-07 08:47:00 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2014-08-07 08:47:00 -0700
commite669830526a0abaf301bf408df69cde33901ac63 (patch)
tree0b6043375006d1754bbd1ab2370b0a0536546cc9 /sound
parentebb067d2f4e2db59b076f9c9cba0375a8ad1e07c (diff)
parent475d5928b79bb78326a645863d46ff95c5e25e5a (diff)
downloadlinux-stericsson-e669830526a0abaf301bf408df69cde33901ac63.tar.gz
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: "This is the main pull request for 3.17. It contains: - misc Cavium Octeon, BCM47xx, BCM63xx and Alchemy updates - MIPS ptrace updates and cleanups - various fixes that will also go to -stable - a number of cleanups and small non-critical fixes. - NUMA support for the Loongson 3. - more support for MSA - support for MAAR - various FP enhancements and fixes" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits) MIPS: jz4740: remove unnecessary null test before debugfs_remove MIPS: Octeon: remove unnecessary null test before debugfs_remove_recursive MIPS: ZBOOT: implement stack protector in compressed boot phase MIPS: mipsreg: remove duplicate MIPS_CONF4_FTLBSETS_SHIFT MIPS: Bonito64: remove a duplicate define MIPS: Malta: initialise MAARs MIPS: Initialise MAARs MIPS: detect presence of MAARs MIPS: define MAAR register accessors & bits MIPS: mark MSA experimental MIPS: Don't build MSA support unless it can be used MIPS: consistently clear MSA flags when starting & copying threads MIPS: 16 byte align MSA vector context MIPS: disable preemption whilst initialising MSA MIPS: ensure MSA gets disabled during boot MIPS: fix read_msa_* & write_msa_* functions on non-MSA toolchains MIPS: fix MSA context for tasks which don't use FP first MIPS: init upper 64b of vector registers when MSA is first used MIPS: save/disable MSA in lose_fpu MIPS: preserve scalar FP CSR when switching vector context ...
Diffstat (limited to 'sound')
-rw-r--r--sound/soc/au1x/psc-ac97.c140
-rw-r--r--sound/soc/au1x/psc-i2s.c100
-rw-r--r--sound/soc/au1x/psc.h22
3 files changed, 131 insertions, 131 deletions
diff --git a/sound/soc/au1x/psc-ac97.c b/sound/soc/au1x/psc-ac97.c
index 986dcec79fa0..84f31e1f9d24 100644
--- a/sound/soc/au1x/psc-ac97.c
+++ b/sound/soc/au1x/psc-ac97.c
@@ -79,28 +79,28 @@ static unsigned short au1xpsc_ac97_read(struct snd_ac97 *ac97,
unsigned short retry, tmo;
unsigned long data;
- au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
- au_sync();
+ __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
+ wmb(); /* drain writebuffer */
retry = AC97_RW_RETRIES;
do {
mutex_lock(&pscdata->lock);
- au_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg),
+ __raw_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg),
AC97_CDC(pscdata));
- au_sync();
+ wmb(); /* drain writebuffer */
tmo = 20;
do {
udelay(21);
- if (au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
+ if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
break;
} while (--tmo);
- data = au_readl(AC97_CDC(pscdata));
+ data = __raw_readl(AC97_CDC(pscdata));
- au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
- au_sync();
+ __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
+ wmb(); /* drain writebuffer */
mutex_unlock(&pscdata->lock);
@@ -119,26 +119,26 @@ static void au1xpsc_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
unsigned int tmo, retry;
- au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
- au_sync();
+ __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
+ wmb(); /* drain writebuffer */
retry = AC97_RW_RETRIES;
do {
mutex_lock(&pscdata->lock);
- au_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff),
+ __raw_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff),
AC97_CDC(pscdata));
- au_sync();
+ wmb(); /* drain writebuffer */
tmo = 20;
do {
udelay(21);
- if (au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
+ if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
break;
} while (--tmo);
- au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
- au_sync();
+ __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
+ wmb(); /* drain writebuffer */
mutex_unlock(&pscdata->lock);
} while (--retry && !tmo);
@@ -149,11 +149,11 @@ static void au1xpsc_ac97_warm_reset(struct snd_ac97 *ac97)
{
struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
- au_writel(PSC_AC97RST_SNC, AC97_RST(pscdata));
- au_sync();
+ __raw_writel(PSC_AC97RST_SNC, AC97_RST(pscdata));
+ wmb(); /* drain writebuffer */
msleep(10);
- au_writel(0, AC97_RST(pscdata));
- au_sync();
+ __raw_writel(0, AC97_RST(pscdata));
+ wmb(); /* drain writebuffer */
}
static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97)
@@ -162,25 +162,25 @@ static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97)
int i;
/* disable PSC during cold reset */
- au_writel(0, AC97_CFG(au1xpsc_ac97_workdata));
- au_sync();
- au_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata));
- au_sync();
+ __raw_writel(0, AC97_CFG(au1xpsc_ac97_workdata));
+ wmb(); /* drain writebuffer */
+ __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata));
+ wmb(); /* drain writebuffer */
/* issue cold reset */
- au_writel(PSC_AC97RST_RST, AC97_RST(pscdata));
- au_sync();
+ __raw_writel(PSC_AC97RST_RST, AC97_RST(pscdata));
+ wmb(); /* drain writebuffer */
msleep(500);
- au_writel(0, AC97_RST(pscdata));
- au_sync();
+ __raw_writel(0, AC97_RST(pscdata));
+ wmb(); /* drain writebuffer */
/* enable PSC */
- au_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
- au_sync();
+ __raw_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
+ wmb(); /* drain writebuffer */
/* wait for PSC to indicate it's ready */
i = 1000;
- while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i))
+ while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i))
msleep(1);
if (i == 0) {
@@ -189,12 +189,12 @@ static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97)
}
/* enable the ac97 function */
- au_writel(pscdata->cfg | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
- au_sync();
+ __raw_writel(pscdata->cfg | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
+ wmb(); /* drain writebuffer */
/* wait for AC97 core to become ready */
i = 1000;
- while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i))
+ while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i))
msleep(1);
if (i == 0)
printk(KERN_ERR "au1xpsc-ac97: AC97 ctrl not ready\n");
@@ -218,8 +218,8 @@ static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream,
chans = params_channels(params);
- r = ro = au_readl(AC97_CFG(pscdata));
- stat = au_readl(AC97_STAT(pscdata));
+ r = ro = __raw_readl(AC97_CFG(pscdata));
+ stat = __raw_readl(AC97_STAT(pscdata));
/* already active? */
if (stat & (PSC_AC97STAT_TB | PSC_AC97STAT_RB)) {
@@ -252,28 +252,28 @@ static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream,
mutex_lock(&pscdata->lock);
/* disable AC97 device controller first... */
- au_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
- au_sync();
+ __raw_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
+ wmb(); /* drain writebuffer */
/* ...wait for it... */
t = 100;
- while ((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t)
+ while ((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t)
msleep(1);
if (!t)
printk(KERN_ERR "PSC-AC97: can't disable!\n");
/* ...write config... */
- au_writel(r, AC97_CFG(pscdata));
- au_sync();
+ __raw_writel(r, AC97_CFG(pscdata));
+ wmb(); /* drain writebuffer */
/* ...enable the AC97 controller again... */
- au_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
- au_sync();
+ __raw_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
+ wmb(); /* drain writebuffer */
/* ...and wait for ready bit */
t = 100;
- while ((!(au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t)
+ while ((!(__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t)
msleep(1);
if (!t)
@@ -300,21 +300,21 @@ static int au1xpsc_ac97_trigger(struct snd_pcm_substream *substream,
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
- au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
- au_sync();
- au_writel(AC97PCR_START(stype), AC97_PCR(pscdata));
- au_sync();
+ __raw_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
+ wmb(); /* drain writebuffer */
+ __raw_writel(AC97PCR_START(stype), AC97_PCR(pscdata));
+ wmb(); /* drain writebuffer */
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
- au_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata));
- au_sync();
+ __raw_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata));
+ wmb(); /* drain writebuffer */
- while (au_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype))
+ while (__raw_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype))
asm volatile ("nop");
- au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
- au_sync();
+ __raw_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
+ wmb(); /* drain writebuffer */
break;
default:
@@ -398,13 +398,13 @@ static int au1xpsc_ac97_drvprobe(struct platform_device *pdev)
PSC_AC97CFG_DE_ENABLE;
/* preserve PSC clock source set up by platform */
- sel = au_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
- au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
- au_sync();
- au_writel(0, PSC_SEL(wd));
- au_sync();
- au_writel(PSC_SEL_PS_AC97MODE | sel, PSC_SEL(wd));
- au_sync();
+ sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
+ __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
+ wmb(); /* drain writebuffer */
+ __raw_writel(0, PSC_SEL(wd));
+ wmb(); /* drain writebuffer */
+ __raw_writel(PSC_SEL_PS_AC97MODE | sel, PSC_SEL(wd));
+ wmb(); /* drain writebuffer */
/* name the DAI like this device instance ("au1xpsc-ac97.PSCINDEX") */
memcpy(&wd->dai_drv, &au1xpsc_ac97_dai_template,
@@ -433,10 +433,10 @@ static int au1xpsc_ac97_drvremove(struct platform_device *pdev)
snd_soc_unregister_component(&pdev->dev);
/* disable PSC completely */
- au_writel(0, AC97_CFG(wd));
- au_sync();
- au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
- au_sync();
+ __raw_writel(0, AC97_CFG(wd));
+ wmb(); /* drain writebuffer */
+ __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
+ wmb(); /* drain writebuffer */
au1xpsc_ac97_workdata = NULL; /* MDEV */
@@ -449,12 +449,12 @@ static int au1xpsc_ac97_drvsuspend(struct device *dev)
struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
/* save interesting registers and disable PSC */
- wd->pm[0] = au_readl(PSC_SEL(wd));
+ wd->pm[0] = __raw_readl(PSC_SEL(wd));
- au_writel(0, AC97_CFG(wd));
- au_sync();
- au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
- au_sync();
+ __raw_writel(0, AC97_CFG(wd));
+ wmb(); /* drain writebuffer */
+ __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
+ wmb(); /* drain writebuffer */
return 0;
}
@@ -464,8 +464,8 @@ static int au1xpsc_ac97_drvresume(struct device *dev)
struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
/* restore PSC clock config */
- au_writel(wd->pm[0] | PSC_SEL_PS_AC97MODE, PSC_SEL(wd));
- au_sync();
+ __raw_writel(wd->pm[0] | PSC_SEL_PS_AC97MODE, PSC_SEL(wd));
+ wmb(); /* drain writebuffer */
/* after this point the ac97 core will cold-reset the codec.
* During cold-reset the PSC is reinitialized and the last
diff --git a/sound/soc/au1x/psc-i2s.c b/sound/soc/au1x/psc-i2s.c
index fe923a7bdc39..814beffc56f2 100644
--- a/sound/soc/au1x/psc-i2s.c
+++ b/sound/soc/au1x/psc-i2s.c
@@ -120,10 +120,10 @@ static int au1xpsc_i2s_hw_params(struct snd_pcm_substream *substream,
unsigned long stat;
/* check if the PSC is already streaming data */
- stat = au_readl(I2S_STAT(pscdata));
+ stat = __raw_readl(I2S_STAT(pscdata));
if (stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB)) {
/* reject parameters not currently set up in hardware */
- cfgbits = au_readl(I2S_CFG(pscdata));
+ cfgbits = __raw_readl(I2S_CFG(pscdata));
if ((PSC_I2SCFG_GET_LEN(cfgbits) != params->msbits) ||
(params_rate(params) != pscdata->rate))
return -EINVAL;
@@ -149,33 +149,33 @@ static int au1xpsc_i2s_configure(struct au1xpsc_audio_data *pscdata)
unsigned long tmo;
/* bring PSC out of sleep, and configure I2S unit */
- au_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
- au_sync();
+ __raw_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
+ wmb(); /* drain writebuffer */
tmo = 1000000;
- while (!(au_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_SR) && tmo)
+ while (!(__raw_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_SR) && tmo)
tmo--;
if (!tmo)
goto psc_err;
- au_writel(0, I2S_CFG(pscdata));
- au_sync();
- au_writel(pscdata->cfg | PSC_I2SCFG_DE_ENABLE, I2S_CFG(pscdata));
- au_sync();
+ __raw_writel(0, I2S_CFG(pscdata));
+ wmb(); /* drain writebuffer */
+ __raw_writel(pscdata->cfg | PSC_I2SCFG_DE_ENABLE, I2S_CFG(pscdata));
+ wmb(); /* drain writebuffer */
/* wait for I2S controller to become ready */
tmo = 1000000;
- while (!(au_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_DR) && tmo)
+ while (!(__raw_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_DR) && tmo)
tmo--;
if (tmo)
return 0;
psc_err:
- au_writel(0, I2S_CFG(pscdata));
- au_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata));
- au_sync();
+ __raw_writel(0, I2S_CFG(pscdata));
+ __raw_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata));
+ wmb(); /* drain writebuffer */
return -ETIMEDOUT;
}
@@ -187,26 +187,26 @@ static int au1xpsc_i2s_start(struct au1xpsc_audio_data *pscdata, int stype)
ret = 0;
/* if both TX and RX are idle, configure the PSC */
- stat = au_readl(I2S_STAT(pscdata));
+ stat = __raw_readl(I2S_STAT(pscdata));
if (!(stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB))) {
ret = au1xpsc_i2s_configure(pscdata);
if (ret)
goto out;
}
- au_writel(I2SPCR_CLRFIFO(stype), I2S_PCR(pscdata));
- au_sync();
- au_writel(I2SPCR_START(stype), I2S_PCR(pscdata));
- au_sync();
+ __raw_writel(I2SPCR_CLRFIFO(stype), I2S_PCR(pscdata));
+ wmb(); /* drain writebuffer */
+ __raw_writel(I2SPCR_START(stype), I2S_PCR(pscdata));
+ wmb(); /* drain writebuffer */
/* wait for start confirmation */
tmo = 1000000;
- while (!(au_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo)
+ while (!(__raw_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo)
tmo--;
if (!tmo) {
- au_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata));
- au_sync();
+ __raw_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata));
+ wmb(); /* drain writebuffer */
ret = -ETIMEDOUT;
}
out:
@@ -217,21 +217,21 @@ static int au1xpsc_i2s_stop(struct au1xpsc_audio_data *pscdata, int stype)
{
unsigned long tmo, stat;
- au_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata));
- au_sync();
+ __raw_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata));
+ wmb(); /* drain writebuffer */
/* wait for stop confirmation */
tmo = 1000000;
- while ((au_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo)
+ while ((__raw_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo)
tmo--;
/* if both TX and RX are idle, disable PSC */
- stat = au_readl(I2S_STAT(pscdata));
+ stat = __raw_readl(I2S_STAT(pscdata));
if (!(stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB))) {
- au_writel(0, I2S_CFG(pscdata));
- au_sync();
- au_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata));
- au_sync();
+ __raw_writel(0, I2S_CFG(pscdata));
+ wmb(); /* drain writebuffer */
+ __raw_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata));
+ wmb(); /* drain writebuffer */
}
return 0;
}
@@ -332,12 +332,12 @@ static int au1xpsc_i2s_drvprobe(struct platform_device *pdev)
/* preserve PSC clock source set up by platform (dev.platform_data
* is already occupied by soc layer)
*/
- sel = au_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
- au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
- au_sync();
- au_writel(PSC_SEL_PS_I2SMODE | sel, PSC_SEL(wd));
- au_writel(0, I2S_CFG(wd));
- au_sync();
+ sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
+ __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
+ wmb(); /* drain writebuffer */
+ __raw_writel(PSC_SEL_PS_I2SMODE | sel, PSC_SEL(wd));
+ __raw_writel(0, I2S_CFG(wd));
+ wmb(); /* drain writebuffer */
/* preconfigure: set max rx/tx fifo depths */
wd->cfg |= PSC_I2SCFG_RT_FIFO8 | PSC_I2SCFG_TT_FIFO8;
@@ -364,10 +364,10 @@ static int au1xpsc_i2s_drvremove(struct platform_device *pdev)
snd_soc_unregister_component(&pdev->dev);
- au_writel(0, I2S_CFG(wd));
- au_sync();
- au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
- au_sync();
+ __raw_writel(0, I2S_CFG(wd));
+ wmb(); /* drain writebuffer */
+ __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
+ wmb(); /* drain writebuffer */
return 0;
}
@@ -378,12 +378,12 @@ static int au1xpsc_i2s_drvsuspend(struct device *dev)
struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
/* save interesting register and disable PSC */
- wd->pm[0] = au_readl(PSC_SEL(wd));
+ wd->pm[0] = __raw_readl(PSC_SEL(wd));
- au_writel(0, I2S_CFG(wd));
- au_sync();
- au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
- au_sync();
+ __raw_writel(0, I2S_CFG(wd));
+ wmb(); /* drain writebuffer */
+ __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
+ wmb(); /* drain writebuffer */
return 0;
}
@@ -393,12 +393,12 @@ static int au1xpsc_i2s_drvresume(struct device *dev)
struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
/* select I2S mode and PSC clock */
- au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
- au_sync();
- au_writel(0, PSC_SEL(wd));
- au_sync();
- au_writel(wd->pm[0], PSC_SEL(wd));
- au_sync();
+ __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
+ wmb(); /* drain writebuffer */
+ __raw_writel(0, PSC_SEL(wd));
+ wmb(); /* drain writebuffer */
+ __raw_writel(wd->pm[0], PSC_SEL(wd));
+ wmb(); /* drain writebuffer */
return 0;
}
diff --git a/sound/soc/au1x/psc.h b/sound/soc/au1x/psc.h
index b16b2e02e0c9..74dffeb641fa 100644
--- a/sound/soc/au1x/psc.h
+++ b/sound/soc/au1x/psc.h
@@ -27,16 +27,16 @@ struct au1xpsc_audio_data {
};
/* easy access macros */
-#define PSC_CTRL(x) ((unsigned long)((x)->mmio) + PSC_CTRL_OFFSET)
-#define PSC_SEL(x) ((unsigned long)((x)->mmio) + PSC_SEL_OFFSET)
-#define I2S_STAT(x) ((unsigned long)((x)->mmio) + PSC_I2SSTAT_OFFSET)
-#define I2S_CFG(x) ((unsigned long)((x)->mmio) + PSC_I2SCFG_OFFSET)
-#define I2S_PCR(x) ((unsigned long)((x)->mmio) + PSC_I2SPCR_OFFSET)
-#define AC97_CFG(x) ((unsigned long)((x)->mmio) + PSC_AC97CFG_OFFSET)
-#define AC97_CDC(x) ((unsigned long)((x)->mmio) + PSC_AC97CDC_OFFSET)
-#define AC97_EVNT(x) ((unsigned long)((x)->mmio) + PSC_AC97EVNT_OFFSET)
-#define AC97_PCR(x) ((unsigned long)((x)->mmio) + PSC_AC97PCR_OFFSET)
-#define AC97_RST(x) ((unsigned long)((x)->mmio) + PSC_AC97RST_OFFSET)
-#define AC97_STAT(x) ((unsigned long)((x)->mmio) + PSC_AC97STAT_OFFSET)
+#define PSC_CTRL(x) ((x)->mmio + PSC_CTRL_OFFSET)
+#define PSC_SEL(x) ((x)->mmio + PSC_SEL_OFFSET)
+#define I2S_STAT(x) ((x)->mmio + PSC_I2SSTAT_OFFSET)
+#define I2S_CFG(x) ((x)->mmio + PSC_I2SCFG_OFFSET)
+#define I2S_PCR(x) ((x)->mmio + PSC_I2SPCR_OFFSET)
+#define AC97_CFG(x) ((x)->mmio + PSC_AC97CFG_OFFSET)
+#define AC97_CDC(x) ((x)->mmio + PSC_AC97CDC_OFFSET)
+#define AC97_EVNT(x) ((x)->mmio + PSC_AC97EVNT_OFFSET)
+#define AC97_PCR(x) ((x)->mmio + PSC_AC97PCR_OFFSET)
+#define AC97_RST(x) ((x)->mmio + PSC_AC97RST_OFFSET)
+#define AC97_STAT(x) ((x)->mmio + PSC_AC97STAT_OFFSET)
#endif