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authorPaulo Zanoni <paulo.r.zanoni@intel.com>2014-07-04 11:50:31 -0300
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-07-23 07:05:32 +0200
commitd49bdb0e1054d022cc6f88fcecf9c79bae66eab0 (patch)
treedb3e2bc2ce5e819705c1ebf21e10bec934dce8ad /drivers/gpu/drm/i915/intel_drv.h
parentc5107b875a84f0b25d1d6b8fbc9acb22440b746f (diff)
downloadlinux-stericsson-d49bdb0e1054d022cc6f88fcecf9c79bae66eab0.tar.gz
drm/i915: extract and improve gen8_irq_power_well_post_enable
Move it from hsw_power_well_post_enable() (intel_pm.c) to i915_irq.c so we can reuse the nice IRQ macros we have there. The main difference is that now we're going to check if the IIR register is non-zero when we try to re-enable the interrupts. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_drv.h')
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9d97a50cae4b..bf415df11389 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -693,6 +693,7 @@ void intel_runtime_pm_disable_interrupts(struct drm_device *dev);
void intel_runtime_pm_restore_interrupts(struct drm_device *dev);
int intel_get_crtc_scanline(struct intel_crtc *crtc);
void i9xx_check_fifo_underruns(struct drm_device *dev);
+void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
/* intel_crt.c */