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authorVille Syrjälä <ville.syrjala@linux.intel.com>2014-05-21 14:04:46 +0300
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-05-22 15:06:33 +0200
commit46a55d3016083bf43568a6a20ad95567fb79202d (patch)
tree73b9716b13ea7a566e4c58eb65062ba3d5a72ee8 /drivers/gpu/drm/i915/intel_drv.h
parentd45a0bf549cda7ab77f3ffce6db1b27b7b435316 (diff)
downloadlinux-stericsson-46a55d3016083bf43568a6a20ad95567fb79202d.tar.gz
drm/i915: Wait for pending page flips before enabling/disabling the primary plane
We have to write to the primary plane base address registrer when we enable/disable the primary plane in response to sprite coverage. Those writes will cause the flip counter to increment which could interfere with the detection of CS flip completion. We could end up completing CS flips before the CS has even executed the commands from the ring. To avoid such issues, wait for CS flips to finish before we toggle the primary plane on/off. v2: Rebased due to atomic sprite update changes Testcase: igt/kms_mmio_vs_cs_flip/setplane_vs_cs_flip Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_drv.h')
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index fe2533ba52a9..287b89e97456 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -802,6 +802,8 @@ int valleyview_get_vco(struct drm_i915_private *dev_priv);
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
struct intel_crtc_config *pipe_config);
int intel_format_to_fourcc(int format);
+void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
+
/* intel_dp.c */
void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);