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authorChristian Daudt <csd@broadcom.com>2013-05-09 22:21:01 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2013-05-15 19:39:27 +0100
commit3b656fed6ff65d6d268da9ed0760c2a58d125771 (patch)
tree17ec053049fedb78e072fbafd055e8ba712422b2 /arch/arm/boot/dts/bcm11351.dtsi
parentfaefd550c45d8d314e8f260f21565320355c947f (diff)
downloadlinux-stericsson-3b656fed6ff65d6d268da9ed0760c2a58d125771.tar.gz
ARM: 7716/1: bcm281xx: Add L2 support for Rev A2 chips
Rev A2 SoCs have an unorthodox memory re-mapping and this needs to be reflected in the cache operations. This patch adds new outer cache functions for the l2x0 driver to support this SoC revision. It also adds a new compatible value for the cache to enable this functionality. Updates from V1: - remove section 1 altogether and note that in comments - simplify section selection caused by section 1 removal - BUG_ON just in case section 1 shows up Signed-off-by: Christian Daudt <csd@broadcom.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/boot/dts/bcm11351.dtsi')
-rw-r--r--arch/arm/boot/dts/bcm11351.dtsi8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 41b2c6c33f09..5e48c85abc2f 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -47,10 +47,10 @@
};
L2: l2-cache {
- compatible = "arm,pl310-cache";
- reg = <0x3ff20000 0x1000>;
- cache-unified;
- cache-level = <2>;
+ compatible = "bcm,bcm11351-a2-pl310-cache";
+ reg = <0x3ff20000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
};
timer@35006000 {