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authorRich Felker <dalias@libc.org>2016-10-13 21:51:06 +0000
committerThomas Gleixner <tglx@linutronix.de>2016-10-20 20:10:17 +0200
commita2ce092be34c4951e23104a0bfdec08f9577fada (patch)
tree6e5127dc34b03a3a8c2d61a07c17b34ec9c7a06d
parent1a1891d762d6e64daf07b5be4817e3fbb29e3c59 (diff)
downloadlinux-stericsson-a2ce092be34c4951e23104a0bfdec08f9577fada.tar.gz
of: Add J-Core timer bindings
Signed-off-by: Rich Felker <dalias@libc.org> Acked-by: Rob Herring <robh@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: linux-sh@vger.kernel.org Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Link: http://lkml.kernel.org/r/8b107c292ed8cf8eed0fa283071fc8a930098628.1476393790.git.dalias@libc.org Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
-rw-r--r--Documentation/devicetree/bindings/timer/jcore,pit.txt24
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diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt
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+J-Core Programmable Interval Timer and Clocksource
+
+Required properties:
+
+- compatible: Must be "jcore,pit".
+
+- reg: Memory region(s) for timer/clocksource registers. For SMP,
+ there should be one region per cpu, indexed by the sequential,
+ zero-based hardware cpu number.
+
+- interrupts: An interrupt to assign for the timer. The actual pit
+ core is integrated with the aic and allows the timer interrupt
+ assignment to be programmed by software, but this property is
+ required in order to reserve an interrupt number that doesn't
+ conflict with other devices.
+
+
+Example:
+
+timer@200 {
+ compatible = "jcore,pit";
+ reg = < 0x200 0x30 0x500 0x30 >;
+ interrupts = < 0x48 >;
+};