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authorDinh Nguyen <dinguyen@altera.com>2013-12-03 14:32:10 -0600
committerOlof Johansson <olof@lixom.net>2013-12-03 14:19:53 -0800
commita5c6e87a7b224bdbf57875a9da8f340f5a6abc5a (patch)
tree576ee8ba1d6fae188d433684bed319214c700ae4
parent725dd7eb170af813407ee45409590941a5ac626e (diff)
downloadlinux-stericsson-a5c6e87a7b224bdbf57875a9da8f340f5a6abc5a.tar.gz
arm: dts: socfpga: Change some clocks of gate-clk type to perip-clk
Some of the clocks that were designated gate-clk do not have a gate, so change those clocks to be of periph-clk type. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Olof Johansson <olof@lixom.net>
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi7
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 6d09b8d42fdd..f936476c2753 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -245,14 +245,14 @@
mpu_periph_clk: mpu_periph_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
+ compatible = "altr,socfpga-perip-clk";
clocks = <&mpuclk>;
fixed-divider = <4>;
};
mpu_l2_ram_clk: mpu_l2_ram_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
+ compatible = "altr,socfpga-perip-clk";
clocks = <&mpuclk>;
fixed-divider = <2>;
};
@@ -266,8 +266,9 @@
l3_main_clk: l3_main_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
+ compatible = "altr,socfpga-perip-clk";
clocks = <&mainclk>;
+ fixed-divider = <1>;
};
l3_mp_clk: l3_mp_clk {