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authorLinus Torvalds <torvalds@linux-foundation.org>2020-06-13 10:55:29 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2020-06-13 10:55:29 -0700
commitcfd230b3cfd6f72a6016fb0b319bb63fcc8206cd (patch)
treeccd01d04647458e3bc0c65b50e34a17cd5571ebb
parent56192707bd8330355d3d1746d99e808eca1999d7 (diff)
parentdb227c19e68db353e4cc6c99b6bc86bb24736943 (diff)
downloadlinux-stericsson-cfd230b3cfd6f72a6016fb0b319bb63fcc8206cd.tar.gz
Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm
Pull ARM fixes from Russell King: - fix for "hex" Kconfig default to use 0x0 rather than 0 to allow these to be removed from defconfigs - fix from Ard Biesheuvel for EFI HYP mode booting * tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: ARM: 8985/1: efi/decompressor: deal with HYP mode boot gracefully ARM: 8984/1: Kconfig: set default ZBOOT_ROM_TEXT/BSS value to 0x0
-rw-r--r--arch/arm/Kconfig4
-rw-r--r--arch/arm/boot/compressed/head.S62
2 files changed, 64 insertions, 2 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bbac2867062d..8789e0e96787 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1749,7 +1749,7 @@ config DEPRECATED_PARAM_STRUCT
# TEXT and BSS so we preserve their values in the config files.
config ZBOOT_ROM_TEXT
hex "Compressed ROM boot loader base address"
- default "0"
+ default 0x0
help
The physical address at which the ROM-able zImage is to be
placed in the target. Platforms which normally make use of
@@ -1760,7 +1760,7 @@ config ZBOOT_ROM_TEXT
config ZBOOT_ROM_BSS
hex "Compressed ROM boot loader BSS address"
- default "0"
+ default 0x0
help
The base address of an area of read/write memory in the target
for the ROM-able zImage which must be available while the
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index c79db44ba128..434a16982e34 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -1410,7 +1410,11 @@ memdump: mov r12, r0
__hyp_reentry_vectors:
W(b) . @ reset
W(b) . @ undef
+#ifdef CONFIG_EFI_STUB
+ W(b) __enter_kernel_from_hyp @ hvc from HYP
+#else
W(b) . @ svc
+#endif
W(b) . @ pabort
W(b) . @ dabort
W(b) __enter_kernel @ hyp
@@ -1429,14 +1433,72 @@ __enter_kernel:
reloc_code_end:
#ifdef CONFIG_EFI_STUB
+__enter_kernel_from_hyp:
+ mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR
+ bic r0, r0, #0x5 @ disable MMU and caches
+ mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR
+ isb
+ b __enter_kernel
+
ENTRY(efi_enter_kernel)
mov r4, r0 @ preserve image base
mov r8, r1 @ preserve DT pointer
+ ARM( adrl r0, call_cache_fn )
+ THUMB( adr r0, call_cache_fn )
+ adr r1, 0f @ clean the region of code we
+ bl cache_clean_flush @ may run with the MMU off
+
+#ifdef CONFIG_ARM_VIRT_EXT
+ @
+ @ The EFI spec does not support booting on ARM in HYP mode,
+ @ since it mandates that the MMU and caches are on, with all
+ @ 32-bit addressable DRAM mapped 1:1 using short descriptors.
+ @
+ @ While the EDK2 reference implementation adheres to this,
+ @ U-Boot might decide to enter the EFI stub in HYP mode
+ @ anyway, with the MMU and caches either on or off.
+ @
+ mrs r0, cpsr @ get the current mode
+ msr spsr_cxsf, r0 @ record boot mode
+ and r0, r0, #MODE_MASK @ are we running in HYP mode?
+ cmp r0, #HYP_MODE
+ bne .Lefi_svc
+
+ mrc p15, 4, r1, c1, c0, 0 @ read HSCTLR
+ tst r1, #0x1 @ MMU enabled at HYP?
+ beq 1f
+
+ @
+ @ When running in HYP mode with the caches on, we're better
+ @ off just carrying on using the cached 1:1 mapping that the
+ @ firmware provided. Set up the HYP vectors so HVC instructions
+ @ issued from HYP mode take us to the correct handler code. We
+ @ will disable the MMU before jumping to the kernel proper.
+ @
+ adr r0, __hyp_reentry_vectors
+ mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR)
+ isb
+ b .Lefi_hyp
+
+ @
+ @ When running in HYP mode with the caches off, we need to drop
+ @ into SVC mode now, and let the decompressor set up its cached
+ @ 1:1 mapping as usual.
+ @
+1: mov r9, r4 @ preserve image base
+ bl __hyp_stub_install @ install HYP stub vectors
+ safe_svcmode_maskall r1 @ drop to SVC mode
+ msr spsr_cxsf, r0 @ record boot mode
+ orr r4, r9, #1 @ restore image base and set LSB
+ b .Lefi_hyp
+.Lefi_svc:
+#endif
mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
tst r0, #0x1 @ MMU enabled?
orreq r4, r4, #1 @ set LSB if not
+.Lefi_hyp:
mov r0, r8 @ DT start
add r1, r8, r2 @ DT end
bl cache_clean_flush