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authorStephan Gerhold <stephan@gerhold.net>2019-11-06 17:58:32 +0100
committerLinus Walleij <linus.walleij@linaro.org>2019-12-11 16:45:34 +0100
commitcdf97f75dde7ddbe7ce2bd1553c4fce65370d5b2 (patch)
treee6046a621f2caea7c0f27ede84d2244fb93cead6
parent9c2d76105a77682426345cc591d3774048f883d1 (diff)
downloadlinux-stericsson-cdf97f75dde7ddbe7ce2bd1553c4fce65370d5b2.tar.gz
drm/mcde: dsi: Delay start of video stream generator
The initialization order for DSI video mode is important - if we enable the video stream generator (VSG) before the MCDE DSI formatter starts sending pixel data, it will immediately run into an error and disable itself again. Avoid this problem by delaying the activation of the VSG until the MCDE DSI formatter is properly set up and running (i.e. when mcde_dsi_bridge_enable() is called). Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r--drivers/gpu/drm/mcde/mcde_dsi.c13
1 files changed, 8 insertions, 5 deletions
diff --git a/drivers/gpu/drm/mcde/mcde_dsi.c b/drivers/gpu/drm/mcde/mcde_dsi.c
index c7956c92b51b..4710f23b2966 100644
--- a/drivers/gpu/drm/mcde/mcde_dsi.c
+++ b/drivers/gpu/drm/mcde/mcde_dsi.c
@@ -583,11 +583,6 @@ static void mcde_dsi_setup_video_mode(struct mcde_dsi *d,
val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC;
val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA;
writel(val, d->regs + DSI_VID_MODE_STS_CTL);
-
- /* Enable video mode */
- val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);
- val |= DSI_MCTL_MAIN_DATA_CTL_VID_EN;
- writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
}
static void mcde_dsi_start(struct mcde_dsi *d)
@@ -699,6 +694,14 @@ static void mcde_dsi_start(struct mcde_dsi *d)
static void mcde_dsi_bridge_enable(struct drm_bridge *bridge)
{
struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);
+ u32 val;
+
+ if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
+ /* Enable video mode */
+ val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);
+ val |= DSI_MCTL_MAIN_DATA_CTL_VID_EN;
+ writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
+ }
dev_info(d->dev, "enable DSI master\n");
};