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authorMurali Karicheri <m-karicheri2@ti.com>2011-11-15 01:42:06 +0530
committerSekhar Nori <nsekhar@ti.com>2011-12-05 16:47:14 +0530
commit8f9a0981aca6bd454ef2a4bdac510af0f6e55bd4 (patch)
treeac6fe47392799e2d7476c5dfd79801d2f89b96b5 /arch
parent5611cc4572e889b62a7b4c72a413536bf6a9c416 (diff)
downloadvexpress-lsk-8f9a0981aca6bd454ef2a4bdac510af0f6e55bd4.tar.gz
ARM: davinci: psc: fix incorrect mask
There are 5 LSB bits defined in PDSTAT and the code currently uses a mask of 1 bit to check the status. Use a proper mask per the hardware specification. While at it, use a #define for the mask to improve readability. Reviewed-by: Sergei Shtylyov <sshtylyov@mvista.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h1
-rw-r--r--arch/arm/mach-davinci/psc.c2
2 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index fa59c097223..8bf279a88b4 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -244,6 +244,7 @@
#define PSC_STATE_ENABLE 3
#define MDSTAT_STATE_MASK 0x3f
+#define PDSTAT_STATE_MASK 0x1f
#define MDCTL_FORCE BIT(31)
#ifndef __ASSEMBLER__
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index 1fb6bdff38c..a0e17707c98 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -80,7 +80,7 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
__raw_writel(mdctl, psc_base + MDCTL + 4 * id);
pdstat = __raw_readl(psc_base + PDSTAT);
- if ((pdstat & 0x00000001) == 0) {
+ if ((pdstat & PDSTAT_STATE_MASK) == 0) {
pdctl1 = __raw_readl(psc_base + PDCTL1);
pdctl1 |= 0x1;
__raw_writel(pdctl1, psc_base + PDCTL1);