aboutsummaryrefslogtreecommitdiff
path: root/arch/sh/Kconfig.cpu
diff options
context:
space:
mode:
authorPaul Mundt <lethal@linux-sh.org>2009-03-17 17:49:49 +0900
committerPaul Mundt <lethal@linux-sh.org>2009-03-17 17:49:49 +0900
commit8263a67e169fdf0d06d172acbf6c03ae172a69d4 (patch)
treecdfefd2d72c7854101287a9e39e3ad97cad6cb5b /arch/sh/Kconfig.cpu
parentda78800632197ac12adcdefbf09991d82adb8201 (diff)
downloadvexpress-lsk-8263a67e169fdf0d06d172acbf6c03ae172a69d4.tar.gz
sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores.
This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores that implement the PTAEX register and respective functionality. Presently only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs). The main change is in how the PTE is written out when loading the entry in to the TLB, as well as in how the TLB entry is selectively flushed. While SH-X2 extended mode splits out the memory-mapped U and I-TLB data arrays for extra bits, extended ASID mode splits out the address arrays. While we don't use the memory-mapped data array access, the address array accesses are necessary for selective TLB flushes, so these are implemented newly and replace the generic SH-4 implementation. With this, TLB flushes in switch_mm() are almost non-existent on newer parts. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/Kconfig.cpu')
-rw-r--r--arch/sh/Kconfig.cpu3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/sh/Kconfig.cpu b/arch/sh/Kconfig.cpu
index 0e27fe3b182..c7d704381a6 100644
--- a/arch/sh/Kconfig.cpu
+++ b/arch/sh/Kconfig.cpu
@@ -104,6 +104,9 @@ config CPU_HAS_SR_RB
config CPU_HAS_PTEA
bool
+config CPU_HAS_PTEAEX
+ bool
+
config CPU_HAS_DSP
bool