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authorRalf Baechle <ralf@linux-mips.org>2012-12-20 12:47:51 +0100
committerRalf Baechle <ralf@linux-mips.org>2012-12-27 16:27:35 +0100
commit9120963578320532dfb3a9a7947e8d05b39900b5 (patch)
tree3a94527080e7013b976be1820e633985e4fe25bb /arch/mips
parent4457af67337112733b65a66c3d56ca5518e1adbb (diff)
downloadvexpress-lsk-9120963578320532dfb3a9a7947e8d05b39900b5.tar.gz
Revert "MIPS: Optimise TLB handlers for MIPS32/64 R2 cores."
This reverts commit ff401e52100dcdc85e572d1ad376d3307b3fe28e. This breaks on MIPS64 R2 cores such as Broadcom's.
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/mm/tlbex.c16
1 files changed, 0 insertions, 16 deletions
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 05613355627..1c8ac49ec72 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -976,13 +976,6 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
#endif
uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
-
- if (cpu_has_mips_r2) {
- uasm_i_ext(p, tmp, tmp, PGDIR_SHIFT, (32 - PGDIR_SHIFT));
- uasm_i_ins(p, ptr, tmp, PGD_T_LOG2, (32 - PGDIR_SHIFT));
- return;
- }
-
uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
@@ -1018,15 +1011,6 @@ static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx)
static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
{
- if (cpu_has_mips_r2) {
- /* PTE ptr offset is obtained from BadVAddr */
- UASM_i_MFC0(p, tmp, C0_BADVADDR);
- UASM_i_LW(p, ptr, 0, ptr);
- uasm_i_ext(p, tmp, tmp, PAGE_SHIFT+1, PGDIR_SHIFT-PAGE_SHIFT-1);
- uasm_i_ins(p, ptr, tmp, PTE_T_LOG2+1, PGDIR_SHIFT-PAGE_SHIFT-1);
- return;
- }
-
/*
* Bug workaround for the Nevada. It seems as if under certain
* circumstances the move from cp0_context might produce a