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authorWill Deacon <will.deacon@arm.com>2011-03-25 13:12:23 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-03-26 10:06:09 +0000
commitd25d3b4c4d0e27975ee659a64b6d29f02fdbfde4 (patch)
tree649a912d82c53b372389eea0e4ea29f3a85bf201 /arch/arm/kernel/perf_event_v7.c
parentfb4fe87d79511398a68000d2100c825f54b51652 (diff)
downloadvexpress-lsk-d25d3b4c4d0e27975ee659a64b6d29f02fdbfde4.tar.gz
ARM: 6833/1: perf: add required isbs() to ARMv7 backend
The ARMv7 architecture does not guarantee that effects from co-processor writes are immediately visible to following instructions. This patch adds two isbs to the ARMv7 perf code: (1) Immediately after selecting an event register, so that the PMU state following this instruction is consistent with the new event. (2) Immediately before writing to the PMCR, so that any previous writes to the PMU have taken effect before (typically) enabling the counters. Acked-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/kernel/perf_event_v7.c')
-rw-r--r--arch/arm/kernel/perf_event_v7.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 2e1402556fa..d6c9dcd1979 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -466,6 +466,7 @@ static inline unsigned long armv7_pmnc_read(void)
static inline void armv7_pmnc_write(unsigned long val)
{
val &= ARMV7_PMNC_MASK;
+ isb();
asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val));
}
@@ -502,6 +503,7 @@ static inline int armv7_pmnc_select_counter(unsigned int idx)
val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK;
asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
+ isb();
return idx;
}