path: root/Documentation
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authorNicolas Pitre <nicolas.pitre@linaro.org>2012-05-02 20:56:52 -0400
committerJon Medhurst <tixy@linaro.org>2013-07-01 11:05:06 +0100
commitbd2bf7cdad1fac1918a7fa9e576ebe1a0c7605ca (patch)
treece2cc1f1bfc2937a141ec67c6e936ec7a24ccad5 /Documentation
parent983b26177be95457be52e0a001893b7de4e0d4f3 (diff)
ARM: vexpress: introduce DCSCB support
This adds basic CPU and cluster reset controls on RTSM for the A15x4-A7x4 model configuration using the Dual Cluster System Configuration Block (DCSCB). The cache coherency interconnect (CCI) is not handled yet. Signed-off-by: Nicolas Pitre <nico@linaro.org> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Pawel Moll <pawel.moll@arm.com>
Diffstat (limited to 'Documentation')
1 files changed, 19 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt b/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt
new file mode 100644
index 00000000000..3b8fbf3c00c
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt
@@ -0,0 +1,19 @@
+ARM Dual Cluster System Configuration Block
+The Dual Cluster System Configuration Block (DCSCB) provides basic
+functionality for controlling clocks, resets and configuration pins in
+the Dual Cluster System implemented by the Real-Time System Model (RTSM).
+Required properties:
+- compatible : should be "arm,rtsm,dcscb"
+- reg : physical base address and the size of the registers window
+ dcscb@60000000 {
+ compatible = "arm,rtsm,dcscb";
+ reg = <0x60000000 0x1000>;
+ };