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authorDave Martin <dave.martin@linaro.org>2013-02-15 16:15:10 +0000
committerAndrey Konovalov <andrey.konovalov@linaro.org>2013-05-25 13:23:53 +0400
commitfcdca1fe734d6d58771636873c1b292e6de13383 (patch)
tree9d4253db51037e8493af5edc390cec81a319d4c2
parentf70071232012ce08084753e26b4f5b26a46c4ad3 (diff)
downloadvexpress-lsk-fcdca1fe734d6d58771636873c1b292e6de13383.tar.gz
ARM: perf: [WIP] Skip PMU register save/restore when no active counters
This patch checks whether any counters are active in the PMU's per- CPU event_mask before attempting save/restore. In practice, this means that the save/restore is skipped if there is no active perf session. If there are no active counters, nothing is saved or restored. The PMU is still reset and quiesced on the restore path, as previously. Signed-off-by: Dave Martin <dave.martin@linaro.org>
-rw-r--r--arch/arm/kernel/perf_event_v7.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 24e195a00af..7e38f1fa712 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -1117,6 +1117,9 @@ static void armv7pmu_save_regs(struct arm_pmu *pmu,
if (!cpupmu->active)
return;
+ if (!*cpupmu->cpu_hw_events.used_mask)
+ return;
+
if (!__v7_pmu_save_reg(cpupmu, PMCR) & ARMV7_PMNC_E)
return;
@@ -1148,6 +1151,9 @@ static void armv7pmu_restore_regs(struct arm_pmu *pmu,
if (!cpupmu->active)
return;
+ if (!*cpupmu->cpu_hw_events.used_mask)
+ return;
+
pmcr = __v7_pmu_read_logical(cpupmu, PMCR);
if (!pmcr & ARMV7_PMNC_E)
return;