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authorPeter Zijlstra <a.p.zijlstra@chello.nl>2011-11-15 10:51:15 +0100
committerIngo Molnar <mingo@elte.hu>2011-12-05 09:32:38 +0100
commit6a600a8b8749566a7d81ad75dcb8bf5342b5a39a (patch)
tree87a29c4aae1e1451436bbc7320310ed145e442be
parent4a1dba72384193753e44e15d9d05a50be6587271 (diff)
downloadvexpress-lsk-6a600a8b8749566a7d81ad75dcb8bf5342b5a39a.tar.gz
perf, x86: Disable PEBS on SandyBridge chips
Cc: Stephane Eranian <eranian@google.com> Cc: stable@kernel.org Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Signed-off-by: Ingo Molnar <mingo@elte.hu>
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 2be5ebe9987..8d601b18bf9 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1545,6 +1545,13 @@ static void intel_clovertown_quirks(void)
x86_pmu.pebs_constraints = NULL;
}
+static void intel_sandybridge_quirks(void)
+{
+ printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");
+ x86_pmu.pebs = 0;
+ x86_pmu.pebs_constraints = NULL;
+}
+
__init int intel_pmu_init(void)
{
union cpuid10_edx edx;
@@ -1694,6 +1701,7 @@ __init int intel_pmu_init(void)
break;
case 42: /* SandyBridge */
+ x86_pmu.quirks = intel_sandybridge_quirks;
case 45: /* SandyBridge, "Romely-EP" */
memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
sizeof(hw_cache_event_ids));