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authorMarc Zyngier <marc.zyngier@arm.com>2013-08-29 11:08:23 +0100
committerGleb Natapov <gleb@redhat.com>2013-08-30 16:12:16 +0300
commit6545eae3d7a1b6dc2edb8ede9107998aee1207ef (patch)
treec7d47b4095192db5a10f4b3c91937d42c89c88f6 /virt
parent986af8e0789a41ac4844e6eefed4a33e86524918 (diff)
downloadlinux-6545eae3d7a1b6dc2edb8ede9107998aee1207ef.tar.gz
ARM: KVM: vgic: fix GICD_ICFGRn access
All the code in handle_mmio_cfg_reg() assumes the offset has been shifted right to accomodate for the 2:1 bit compression, but this is only done when getting the register address. Shift the offset early so the code works mostly unchanged. Reported-by: Zhaobo (Bob, ERC) <zhaobo@huawei.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Gleb Natapov <gleb@redhat.com>
Diffstat (limited to 'virt')
-rw-r--r--virt/kvm/arm/vgic.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c
index a2d478aec04..902789ff4ab 100644
--- a/virt/kvm/arm/vgic.c
+++ b/virt/kvm/arm/vgic.c
@@ -541,8 +541,12 @@ static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu,
struct kvm_exit_mmio *mmio, phys_addr_t offset)
{
u32 val;
- u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg,
- vcpu->vcpu_id, offset >> 1);
+ u32 *reg;
+
+ offset >>= 1;
+ reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg,
+ vcpu->vcpu_id, offset);
+
if (offset & 2)
val = *reg >> 16;
else