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authorJoachim Deguara <joachim.deguara@amd.com>2007-03-16 15:01:36 +0100
committerJaroslav Kysela <perex@suse.cz>2007-03-16 15:02:15 +0100
commit5f1545bc45a33361d6bb2fb44af7c35bcd733b9d (patch)
tree2097dce16d2a7e15c2c9dba0ab99e59d5bd6be45 /sound
parenta8a5d06775f54ab2d23ad6455db399c15a664feb (diff)
downloadlinux-5f1545bc45a33361d6bb2fb44af7c35bcd733b9d.tar.gz
[ALSA] hda-intel - Fix HDA buffer alignment
From the HDA spec it appears that the buffers written to the BDL and sent to a codec must be 128 byte aligned (section 4.5.1). The alignment was not happening especially when playing 6 channels. This patch set the alignment of buffers and periods to 128 bytes. Signed-off-by: Joachim Deguara <joachim.deguara@amd.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@suse.cz>
Diffstat (limited to 'sound')
-rw-r--r--sound/pci/hda/hda_intel.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 13e4837b5ae..1672cace1ae 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -1087,6 +1087,10 @@ static int azx_pcm_open(struct snd_pcm_substream *substream)
runtime->hw.rates = hinfo->rates;
snd_pcm_limit_hw_rates(runtime);
snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
+ snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
+ 128);
+ snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
+ 128);
if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
azx_release_device(azx_dev);
mutex_unlock(&chip->open_mutex);