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authorPeter Zijlstra <peterz@infradead.org>2011-04-22 23:37:06 +0200
committerIngo Molnar <mingo@elte.hu>2011-07-01 11:06:38 +0200
commit89d6c0b5bdbb1927775584dcf532d98b3efe1477 (patch)
tree89ec2fb7944dbf79ccb5d1a47f6117cd9c8b617f /samples
parentb79e8941fb9af07d810da91b4e29da2bba331b6e (diff)
downloadlinux-89d6c0b5bdbb1927775584dcf532d98b3efe1477.tar.gz
perf, arch: Add generic NODE cache events
Add a NODE level to the generic cache events which is used to measure local vs remote memory accesses. Like all other cache events, an ACCESS is HIT+MISS, if there is no way to distinguish between reads and writes do reads only etc.. The below needs filling out for !x86 (which I filled out with unsupported events). I'm fairly sure ARM can leave it like that since it doesn't strike me as an architecture that even has NUMA support. SH might have something since it does appear to have some NUMA bits. Sparc64, PowerPC and MIPS certainly want a good look there since they clearly are NUMA capable. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: David Miller <davem@davemloft.net> Cc: Anton Blanchard <anton@samba.org> Cc: David Daney <ddaney@caviumnetworks.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Will Deacon <will.deacon@arm.com> Cc: Robert Richter <robert.richter@amd.com> Cc: Stephane Eranian <eranian@google.com> Link: http://lkml.kernel.org/r/1303508226.4865.8.camel@laptop Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'samples')
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