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authorGavin Shan <shangw@linux.vnet.ibm.com>2013-04-04 16:54:30 +0000
committerBjorn Helgaas <bhelgaas@google.com>2013-04-23 09:50:30 -0600
commite375b561817d9ae098cc4296a729fc88924a0159 (patch)
tree7cd6f54166d29a1b7c612e407d57ce79b1024610 /include
parent703860ed4e36ded696bd44af6107243fdedfb746 (diff)
downloadlinux-e375b561817d9ae098cc4296a729fc88924a0159.tar.gz
PCI: Cache MSI/MSI-X capability offsets in struct pci_dev
The patch caches the MSI and MSI-X capability offset in PCI device (struct pci_dev) so that we needn't read it from the config space upon enabling or disabling MSI or MSI-X interrupts. [bhelgaas: moved pm_cap size change to separate patch] Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/pci.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 9587d4d1927..b73c2460ad5 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -232,6 +232,8 @@ struct pci_dev {
u8 revision; /* PCI revision, low byte of class word */
u8 hdr_type; /* PCI header type (`multi' flag masked out) */
u8 pcie_cap; /* PCI-E capability offset */
+ u8 msi_cap; /* MSI capability offset */
+ u8 msix_cap; /* MSI-X capability offset */
u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
u8 rom_base_reg; /* which config register controls the ROM */
u8 pin; /* which interrupt pin this device uses */