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authorAndi Kleen <ak@suse.de>2005-04-16 15:25:05 -0700
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 15:25:05 -0700
commitc29601e9c1e7893d1755364e350c9188bd56d69f (patch)
tree14813ddce4d8897b40cc8b3a2f76ace3ac58b36f /include/asm-x86_64
parentdc37db4d8cb376bb67c6357c50d707ced3d71c39 (diff)
downloadlinux-c29601e9c1e7893d1755364e350c9188bd56d69f.tar.gz
[PATCH] x86_64: Support constantly ticking TSCs
On Intel Noconas the TSC ticks with a constant frequency. Don't scale the factor used by udelay when cpufreq changes the frequency. This generalizes an earlier patch by Intel for this. Cc: <venkatesh.pallipadi@intel.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-x86_64')
-rw-r--r--include/asm-x86_64/cpufeature.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-x86_64/cpufeature.h b/include/asm-x86_64/cpufeature.h
index 0e47a6d5372..e68ad97a631 100644
--- a/include/asm-x86_64/cpufeature.h
+++ b/include/asm-x86_64/cpufeature.h
@@ -62,6 +62,7 @@
#define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
#define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
#define X86_FEATURE_K8_C (3*32+ 4) /* C stepping K8 */
+#define X86_FEATURE_CONSTANT_TSC (3*32+5) /* TSC runs at constant rate */
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */