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authorAndy Fleming <afleming@freescale.com>2008-02-04 18:27:55 -0600
committerKumar Gala <galak@kernel.crashing.org>2008-02-05 23:34:14 -0600
commit39aef685af431c032ffd2763ec8782b13c32520c (patch)
tree2e6c8761ec9d62521418f6b0b2cf05f8e269407d /include/asm-powerpc/reg_booke.h
parent0367aad1ad5f8085ed15e9e30604f50108a1ea06 (diff)
downloadlinux-39aef685af431c032ffd2763ec8782b13c32520c.tar.gz
[POWERPC] Made FSL Book-E PMC support more generic
Some of the more recent e300 cores have the same performance monitor implementation as the e500. e300 isn't book-e, so the name isn't really appropriate. In preparation for e300 support, rename a bunch of fsl_booke things to say fsl_emb (Freescale Embedded Performance Monitors). Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/asm-powerpc/reg_booke.h')
-rw-r--r--include/asm-powerpc/reg_booke.h62
1 files changed, 0 insertions, 62 deletions
diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h
index 0405ef47981..cf54a3f3175 100644
--- a/include/asm-powerpc/reg_booke.h
+++ b/include/asm-powerpc/reg_booke.h
@@ -9,68 +9,6 @@
#ifndef __ASM_POWERPC_REG_BOOKE_H__
#define __ASM_POWERPC_REG_BOOKE_H__
-#ifndef __ASSEMBLY__
-/* Performance Monitor Registers */
-#define mfpmr(rn) ({unsigned int rval; \
- asm volatile("mfpmr %0," __stringify(rn) \
- : "=r" (rval)); rval;})
-#define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
-#endif /* __ASSEMBLY__ */
-
-/* Freescale Book E Performance Monitor APU Registers */
-#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */
-#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
-#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */
-#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */
-#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
-#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
-#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
-#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
-
-#define PMLCA_FC 0x80000000 /* Freeze Counter */
-#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */
-#define PMLCA_FCU 0x20000000 /* Freeze in User */
-#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */
-#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */
-#define PMLCA_CE 0x04000000 /* Condition Enable */
-
-#define PMLCA_EVENT_MASK 0x007f0000 /* Event field */
-#define PMLCA_EVENT_SHIFT 16
-
-#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */
-#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */
-#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
-#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
-
-#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */
-#define PMLCB_THRESHMUL_SHIFT 8
-
-#define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */
-#define PMLCB_THRESHOLD_SHIFT 0
-
-#define PMRN_PMGC0 0x190 /* PM Global Control 0 */
-
-#define PMGC0_FAC 0x80000000 /* Freeze all Counters */
-#define PMGC0_PMIE 0x40000000 /* Interrupt Enable */
-#define PMGC0_FCECE 0x20000000 /* Freeze countes on
- Enabled Condition or
- Event */
-
-#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */
-#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */
-#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */
-#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */
-#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */
-#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */
-#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */
-#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */
-#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */
-#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */
-#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
-#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */
-#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */
-
-
/* Machine State Register (MSR) Fields */
#define MSR_UCLE (1<<26) /* User-mode cache lock enable */
#define MSR_SPE (1<<25) /* Enable SPE */