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authorJulien CHAUVEAU <julien.chauveau@neo-technologies.fr>2014-11-21 11:08:47 +0100
committerHeiko Stuebner <heiko@sntech.de>2014-11-23 01:55:14 +0100
commit12c0a0e81e2f9c03404a3e095517c022991aad43 (patch)
tree33305edb4c4b0b41169216e012066443f4d99420 /drivers/clk
parentb7bdb7f45e7b848dc2eb50c2d5c5106af68562c4 (diff)
downloadlinux-12c0a0e81e2f9c03404a3e095517c022991aad43.tar.gz
clk: rockchip: fix rk3188 USB HSIC PHY clock divider
The USB HSIC PHY clock divider is set in the register RK2928_CLKSEL_CON(11). Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/rockchip/clk-rk3188.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index c2498697081..22dccc6cd66 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -664,7 +664,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(30), 0, 2, DFLAGS,
RK2928_CLKGATE_CON(3), 6, GFLAGS),
DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0,
- RK2928_CLKGATE_CON(11), 8, 6, DFLAGS),
+ RK2928_CLKSEL_CON(11), 8, 6, DFLAGS),
MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),