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authorHeiko Stuebner <heiko@sntech.de>2011-09-26 10:30:29 +0900
committerKukjin Kim <kgene.kim@samsung.com>2011-09-26 10:30:29 +0900
commit4344646ff127eaea4d58266ccd8fdd2a38fb9672 (patch)
treed0b611ea53778db228cf6dab08b6dbaae8fb0aeb /arch
parentd93dc5c4478c1fd5de85a3e8aece9aad7bbae044 (diff)
downloadlinux-4344646ff127eaea4d58266ccd8fdd2a38fb9672.tar.gz
ARM: S3C2443: Fix bit-reset in setrate of clk_armdiv
The changed statement should set the old armdiv bits to 0 and not everything else, before setting the new value. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-s3c2443/clock.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index a1a7176675b..38058af4897 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -128,7 +128,7 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
unsigned long clkcon0;
clkcon0 = __raw_readl(S3C2443_CLKDIV0);
- clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
+ clkcon0 &= ~S3C2443_CLKDIV0_ARMDIV_MASK;
clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
__raw_writel(clkcon0, S3C2443_CLKDIV0);
}