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authorOndrej Zary <linux@rainbow-software.org>2010-06-08 00:32:49 +0200
committerRafael J. Wysocki <rjw@sisk.pl>2010-06-08 00:32:49 +0200
commit85a0e7539781dad4bfcffd98e72fa9f130f4e40d (patch)
treec64b6526319b3e9c5a8c8592ca96988a3726b9ad /arch/x86/power
parent386f40c86d6c8d5b717ef20620af1a750d0dacb4 (diff)
downloadlinux-85a0e7539781dad4bfcffd98e72fa9f130f4e40d.tar.gz
PM / x86: Save/restore MISC_ENABLE register
Save/restore MISC_ENABLE register on suspend/resume. This fixes OOPS (invalid opcode) on resume from STR on Asus P4P800-VM, which wakes up with MWAIT disabled. Fixes https://bugzilla.kernel.org/show_bug.cgi?id=15385 Signed-off-by: Ondrej Zary <linux@rainbow-software.org> Tested-by: Alan Stern <stern@rowland.harvard.edu> Acked-by: H. Peter Anvin <hpa@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Diffstat (limited to 'arch/x86/power')
-rw-r--r--arch/x86/power/cpu.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c
index 0a979f3e5b8..1290ba54b35 100644
--- a/arch/x86/power/cpu.c
+++ b/arch/x86/power/cpu.c
@@ -105,6 +105,8 @@ static void __save_processor_state(struct saved_context *ctxt)
ctxt->cr4 = read_cr4();
ctxt->cr8 = read_cr8();
#endif
+ ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
+ &ctxt->misc_enable);
}
/* Needed by apm.c */
@@ -152,6 +154,8 @@ static void fix_processor_context(void)
*/
static void __restore_processor_state(struct saved_context *ctxt)
{
+ if (ctxt->misc_enable_saved)
+ wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
/*
* control registers
*/