path: root/arch/x86/include/asm/irq_vectors.h
diff options
authorSuresh Siddha <suresh.b.siddha@intel.com>2010-01-13 16:19:11 -0800
committerH. Peter Anvin <hpa@zytor.com>2010-01-18 10:59:59 -0800
commit6579b474572fd54c583ac074e8e7aaae926c62ef (patch)
treed84740df8c254be8d8875c8caaedf2da3124076a /arch/x86/include/asm/irq_vectors.h
parent722b3654852e48b93367a63f8ada9ee1cd43f2d3 (diff)
x86, irq: Use 0x20 for the IRQ_MOVE_CLEANUP_VECTOR instead of 0x1f
After talking to some more folks inside intel (Peter Anvin, Asit Mallick), the safest option (for future compatibility etc) seen was to use vector 0x20 for IRQ_MOVE_CLEANUP_VECTOR instead of using vector 0x1f (which is documented as reserved vector in the Intel IA32 manuals). Also we don't need to reserve the entire privilege level (all 16 vectors in the priority bucket that IRQ_MOVE_CLEANUP_VECTOR falls into), as the x86 architecture (section 10.9.3 in SDM Vol3a) specifies that with in the priority level, the higher the vector number the higher the priority. And hence we don't need to reserve the complete priority level 0x20-0x2f for the IRQ migration cleanup logic. So change the IRQ_MOVE_CLEANUP_VECTOR to 0x20 and allow 0x21-0x2f to be used for device interrupts. 0x30-0x3f will be used for ISA interrupts (these also can be migrated in the context of IOAPIC and hence need to be at a higher priority level than IRQ_MOVE_CLEANUP_VECTOR). Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> LKML-Reference: <20100114002118.521826763@sbs-t61.sc.intel.com> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Eric W. Biederman <ebiederm@xmission.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/include/asm/irq_vectors.h')
1 files changed, 16 insertions, 31 deletions
diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_vectors.h
index 585a42810cf..8767d99c4f6 100644
--- a/arch/x86/include/asm/irq_vectors.h
+++ b/arch/x86/include/asm/irq_vectors.h
@@ -28,19 +28,22 @@
#define MCE_VECTOR 0x12
- * IDT vectors usable for external interrupt sources start
- * at 0x20:
- * hpa said we can start from 0x1f.
- * 0x1f is documented as reserved. However, the ability for the APIC
- * to generate vectors starting at 0x10 is documented, as is the
- * ability for the CPU to receive any vector number as an interrupt.
- * 0x1f is used for IRQ_MOVE_CLEANUP_VECTOR since that vector needs
- * an entire privilege level (16 vectors) all by itself at a higher
- * priority than any actual device vector. Thus, by placing it in the
- * otherwise-unusable 0x10 privilege level, we avoid wasting a full
- * 16-vector block.
+ * IDT vectors usable for external interrupt sources start at 0x20.
+ * (0x80 is the syscall vector, 0x30-0x3f are for ISA)
+ * We start allocating at 0x21 to spread out vectors evenly between
+ * priority levels. (0x80 is the syscall vector)
+ */
+ * Reserve the lowest usable vector (and hence lowest priority) 0x20 for
+ * triggering cleanup after irq migration. 0x21-0x2f will still be used
+ * for device interrupts.
+ */
#define IA32_SYSCALL_VECTOR 0x80
#ifdef CONFIG_X86_32
@@ -48,17 +51,7 @@
- * Reserve the lowest usable priority level 0x10 - 0x1f for triggering
- * cleanup after irq migration.
- * this overlaps with the reserved range for cpu exceptions so this
- * will need to be changed to 0x20 - 0x2f if the last cpu exception is
- * ever allocated.
- */
- * Vectors 0x20-0x2f are used for ISA interrupts.
+ * Vectors 0x30-0x3f are used for ISA interrupts.
* round up to the next 16-vector boundary
#define IRQ0_VECTOR ((FIRST_EXTERNAL_VECTOR + 16) & ~15)
@@ -132,14 +125,6 @@
#define MCE_SELF_VECTOR 0xeb
- * First APIC vector available to drivers: (vectors 0x30-0xee). We
- * start allocating at 0x31 to spread out vectors evenly between
- * priority levels. (0x80 is the syscall vector)
- */
#define NR_VECTORS 256
#define FPU_IRQ 13