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authorThierry Reding <thierry.reding@avionic-design.de>2012-09-14 16:14:25 +0800
committerThierry Reding <thierry.reding@avionic-design.de>2012-10-05 20:56:39 +0200
commitd1b6886502160eb771aefe21c1f891597138ddfe (patch)
treeeee4f1aade9c3b34878ba849301a196532a9fdd0 /arch/unicore32
parent60ce70285b4d3b933eea15e494a9b35fe85b19b7 (diff)
downloadlinux-d1b6886502160eb771aefe21c1f891597138ddfe.tar.gz
unicore32: pwm: Properly remap memory-mapped registers
Instead of writing to the timer controller registers by dereferencing a pointer to the memory location, properly remap the memory region with a call to ioremap_nocache() and access the registers using writel(). Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Tested-by: Qin Rui <qinrui@mprc.pku.edu.cn>
Diffstat (limited to 'arch/unicore32')
-rw-r--r--arch/unicore32/include/mach/regs-ost.h18
-rw-r--r--arch/unicore32/kernel/pwm.c21
2 files changed, 26 insertions, 13 deletions
diff --git a/arch/unicore32/include/mach/regs-ost.h b/arch/unicore32/include/mach/regs-ost.h
index 7b91fe698ee..4a85fb46384 100644
--- a/arch/unicore32/include/mach/regs-ost.h
+++ b/arch/unicore32/include/mach/regs-ost.h
@@ -33,18 +33,16 @@
* Interrupt Enable Reg OST_OIER
*/
#define OST_OIER (PKUNITY_OST_BASE + 0x001C)
+
/*
- * PWM Pulse Width Control Reg OST_PWMPWCR
- */
-#define OST_PWMPWCR (PKUNITY_OST_BASE + 0x0080)
-/*
- * PWM Duty Cycle Control Reg OST_PWMDCCR
- */
-#define OST_PWMDCCR (PKUNITY_OST_BASE + 0x0084)
-/*
- * PWM Period Control Reg OST_PWMPCR
+ * PWM Registers: IO base address: PKUNITY_OST_BASE + 0x80
+ * PWCR: Pulse Width Control Reg
+ * DCCR: Duty Cycle Control Reg
+ * PCR: Period Control Reg
*/
-#define OST_PWMPCR (PKUNITY_OST_BASE + 0x0088)
+#define OST_PWM_PWCR (0x00)
+#define OST_PWM_DCCR (0x04)
+#define OST_PWM_PCR (0x08)
/*
* Match detected 0 OST_OSSR_M0
diff --git a/arch/unicore32/kernel/pwm.c b/arch/unicore32/kernel/pwm.c
index 4615d51e3ba..885bbcdc253 100644
--- a/arch/unicore32/kernel/pwm.c
+++ b/arch/unicore32/kernel/pwm.c
@@ -27,6 +27,8 @@ struct pwm_device {
struct list_head node;
struct platform_device *pdev;
+ void __iomem *base;
+
const char *label;
struct clk *clk;
int clk_enabled;
@@ -69,9 +71,11 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
* before writing to the registers
*/
clk_enable(pwm->clk);
- OST_PWMPWCR = prescale;
- OST_PWMDCCR = pv - dc;
- OST_PWMPCR = pv;
+
+ writel(prescale, pwm->base + OST_PWM_PWCR);
+ writel(pv - dc, pwm->base + OST_PWM_DCCR);
+ writel(pv, pwm->base + OST_PWM_PCR);
+
clk_disable(pwm->clk);
return 0;
@@ -190,10 +194,19 @@ static struct pwm_device *pwm_probe(struct platform_device *pdev,
goto err_free_clk;
}
+ pwm->base = ioremap_nocache(r->start, resource_size(r));
+ if (pwm->base == NULL) {
+ dev_err(&pdev->dev, "failed to remap memory resource\n");
+ ret = -EADDRNOTAVAIL;
+ goto err_release_mem;
+ }
+
__add_pwm(pwm);
platform_set_drvdata(pdev, pwm);
return pwm;
+err_release_mem:
+ release_mem_region(r->start, resource_size(r));
err_free_clk:
clk_put(pwm->clk);
err_free:
@@ -224,6 +237,8 @@ static int __devexit pwm_remove(struct platform_device *pdev)
list_del(&pwm->node);
mutex_unlock(&pwm_lock);
+ iounmap(pwm->base);
+
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
release_mem_region(r->start, resource_size(r));