aboutsummaryrefslogtreecommitdiff
path: root/arch/powerpc/lib/copypage_power7.S
diff options
context:
space:
mode:
authorMichael Neuling <mikey@neuling.org>2012-06-25 13:33:10 +0000
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2012-07-10 19:17:55 +1000
commitc75df6f96c59beed8632e3aced5fb4faabaa6c5b (patch)
treeb21ce9394028ec4520a71d87391dad8ab29edd67 /arch/powerpc/lib/copypage_power7.S
parent564aa5cfd3e33ef69a5ca6c170a0fe79c6805e52 (diff)
downloadlinux-c75df6f96c59beed8632e3aced5fb4faabaa6c5b.tar.gz
powerpc: Fix usage of register macros getting ready for %r0 change
Anything that uses a constructed instruction (ie. from ppc-opcode.h), need to use the new R0 macro, as %r0 is not going to work. Also convert usages of macros where we are just determining an offset (usually for a load/store), like: std r14,STK_REG(r14)(r1) Can't use STK_REG(r14) as %r14 doesn't work in the STK_REG macro since it's just calculating an offset. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/lib/copypage_power7.S')
-rw-r--r--arch/powerpc/lib/copypage_power7.S28
1 files changed, 14 insertions, 14 deletions
diff --git a/arch/powerpc/lib/copypage_power7.S b/arch/powerpc/lib/copypage_power7.S
index 01e2b5db325..a2126cebb95 100644
--- a/arch/powerpc/lib/copypage_power7.S
+++ b/arch/powerpc/lib/copypage_power7.S
@@ -113,13 +113,13 @@ _GLOBAL(copypage_power7)
#endif
.Lnonvmx_copy:
- std r14,STK_REG(r14)(r1)
- std r15,STK_REG(r15)(r1)
- std r16,STK_REG(r16)(r1)
- std r17,STK_REG(r17)(r1)
- std r18,STK_REG(r18)(r1)
- std r19,STK_REG(r19)(r1)
- std r20,STK_REG(r20)(r1)
+ std r14,STK_REG(R14)(r1)
+ std r15,STK_REG(R15)(r1)
+ std r16,STK_REG(R16)(r1)
+ std r17,STK_REG(R17)(r1)
+ std r18,STK_REG(R18)(r1)
+ std r19,STK_REG(R19)(r1)
+ std r20,STK_REG(R20)(r1)
1: ld r0,0(r4)
ld r5,8(r4)
@@ -157,12 +157,12 @@ _GLOBAL(copypage_power7)
addi r3,r3,128
bdnz 1b
- ld r14,STK_REG(r14)(r1)
- ld r15,STK_REG(r15)(r1)
- ld r16,STK_REG(r16)(r1)
- ld r17,STK_REG(r17)(r1)
- ld r18,STK_REG(r18)(r1)
- ld r19,STK_REG(r19)(r1)
- ld r20,STK_REG(r20)(r1)
+ ld r14,STK_REG(R14)(r1)
+ ld r15,STK_REG(R15)(r1)
+ ld r16,STK_REG(R16)(r1)
+ ld r17,STK_REG(R17)(r1)
+ ld r18,STK_REG(R18)(r1)
+ ld r19,STK_REG(R19)(r1)
+ ld r20,STK_REG(R20)(r1)
addi r1,r1,STACKFRAMESIZE
blr