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authorJayachandran C <jchandra@broadcom.com>2014-04-29 20:07:47 +0530
committerRalf Baechle <ralf@linux-mips.org>2014-05-30 16:48:25 +0200
commite9126418dd7a86bee32d2dae37df403f7f1e2a13 (patch)
treef4ed5bce0aefa196e28535505ea52cab44b6e4ac /arch/mips/netlogic
parenta3deecfaa36662ca2e2104be3c305236cf03efcc (diff)
downloadlinux-e9126418dd7a86bee32d2dae37df403f7f1e2a13.tar.gz
MIPS: Netlogic: Enable access to more than 64GB
The ELPA bit needs to be set in the PAGEGRAIN register to enable access to >64GB physical address. Update reset.S to do this from every hardware thread. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6866/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/netlogic')
-rw-r--r--arch/mips/netlogic/common/reset.S15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
index fda772a8595..13c1bc5b598 100644
--- a/arch/mips/netlogic/common/reset.S
+++ b/arch/mips/netlogic/common/reset.S
@@ -74,6 +74,18 @@
.endm
/*
+ * Allow access to physical mem >64G by enabling ELPA in PAGEGRAIN
+ * register. This is needed before going to C code since the SP can
+ * in this region. Called from all HW threads.
+ */
+.macro xlp_early_mmu_init
+ mfc0 t0, CP0_PAGEMASK, 1
+ li t1, (1 << 29) /* ELPA bit */
+ or t0, t1
+ mtc0 t0, CP0_PAGEMASK, 1
+.endm
+
+/*
* L1D cache has to be flushed before enabling threads in XLP.
* On XLP8xx/XLP3xx, we do a low level flush using processor control
* registers. On XLPII CPUs, usual cache instructions work.
@@ -228,6 +240,8 @@ EXPORT(nlm_boot_siblings)
#endif
mtc0 t1, CP0_STATUS
+ xlp_early_mmu_init
+
/* mark CPU ready */
li t3, CKSEG1ADDR(RESET_DATA_PHYS)
ADDIU t1, t3, BOOT_CPU_READY
@@ -254,6 +268,7 @@ EXPORT(nlm_reset_entry_end)
LEAF(nlm_init_boot_cpu)
#ifdef CONFIG_CPU_XLP
xlp_config_lsu
+ xlp_early_mmu_init
#endif
jr ra
nop