path: root/arch/arm
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authorMagnus Damm <damm+renesas@opensource.se>2015-01-16 10:17:10 +0900
committerSimon Horman <horms+renesas@verge.net.au>2015-01-17 09:28:14 +0900
commit1fbbc3f0c5440a4c674b3d6de0a9dd447666b508 (patch)
treed63e2389b180eae48a20562e985d1f3f7335f179 /arch/arm
parentb0ddb319db3d7a1943445f0de0a45c07a7f3457a (diff)
ARM: shmobile: r8a7778: Instantiate GIC from C board code in legacy builds
As of commit 9a1091ef0017c40a ("irqchip: gic: Support hierarchy irq domain."), Bock-W legacy hangs during boot with: Unable to handle kernel paging request at virtual address cf86a128 pgd = c0004000 [cf86a128] *pgd=6f80041e(bad) Internal error: Oops: 8000000d [#1] SMP ARM CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.19.0-rc4 #1 Hardware name: bockw task: cf823b40 ti: cf824000 task.ti: cf824000 PC is at 0xcf86a128 LR is at request_threaded_irq+0xbc/0x124 This happens because the IRQ numbers of the GIC are now virtual, and no longer match the hardcoded hardware IRQ numbers in the platform board code. To fix this, instantiate the GIC from platform board code when compiling a legacy kernel, like is done for the sh73a0 and r8a7740 legacy code. Follows same style as the r8a7740 legacy GIC fix by Geert Uytterhoeven, thanks to him for the initial work. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm')
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 85fe016d6a8..5d7a0095259 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -586,11 +586,18 @@ void __init r8a7778_init_delay(void)
void __init r8a7778_init_irq_dt(void)
void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
+ void __iomem *gic_dist_base = ioremap_nocache(0xfe438000, 0x1000);
+ void __iomem *gic_cpu_base = ioremap_nocache(0xfe430000, 0x1000);
+ gic_init(0, 29, gic_dist_base, gic_cpu_base);
/* route all interrupts to ARM */
__raw_writel(0x73ffffff, base + INT2NTSR0);
__raw_writel(0xffffffff, base + INT2NTSR1);