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authorNicolas Pitre <nico@cam.org>2008-09-16 13:05:53 -0400
committerNicolas Pitre <nico@cam.org>2009-03-15 21:01:20 -0400
commit5f0fbf9ecaf354fa4bbf266fffdea2ea3d14a0ed (patch)
tree9f0c59760b2bec510519118ddb17d4b15db473f5 /arch/arm/mm/mm.h
parent1522ac3ec95ff0230e7aa516f86b674fdf72866c (diff)
downloadlinux-5f0fbf9ecaf354fa4bbf266fffdea2ea3d14a0ed.tar.gz
[ARM] fixmap support
This is the minimum fixmap interface expected to be implemented by architectures supporting highmem. We have a second level page table already allocated and covering 0xfff00000-0xffffffff because the exception vector page is located at 0xffff0000, and various cache tricks already use some entries above 0xffff0000. Therefore the PTEs covering 0xfff00000-0xfffeffff are free to be used. However the XScale cache flushing code already uses virtual addresses between 0xfffe0000 and 0xfffeffff. So this reserves the 0xfff00000-0xfffdffff range for fixmap stuff. The Documentation/arm/memory.txt information is updated accordingly, including the information about the actual top of DMA memory mapping region which didn't match the code. Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/mm/mm.h')
-rw-r--r--arch/arm/mm/mm.h3
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index 95bbe112965..c4f6f05198e 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -1,7 +1,6 @@
-/* the upper-most page table pointer */
-
#ifdef CONFIG_MMU
+/* the upper-most page table pointer */
extern pmd_t *top_pmd;
#define TOP_PTE(x) pte_offset_kernel(top_pmd, x)