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authorMarc Zyngier <marc.zyngier@arm.com>2013-04-12 14:00:16 +0100
committerChristoffer Dall <cdall@cs.columbia.edu>2013-04-16 16:21:25 -0700
commit865499ea90d399e0682bcce3ae7af24277633699 (patch)
tree4f43ed01655ccf1241187da59c8c0cee44f26558 /arch/arm/include
parentca46e10fb239d4646cb19620695473f252a6ffc7 (diff)
downloadlinux-865499ea90d399e0682bcce3ae7af24277633699.tar.gz
ARM: KVM: fix L_PTE_S2_RDWR to actually be Read/Write
Looks like our L_PTE_S2_RDWR definition is slightly wrong, and is actually write only (see ARM ARM Table B3-9, Stage 2 control of access permissions). Didn't make a difference for normal pages, as we OR the flags together, but I'm still wondering how it worked for Stage-2 mapped devices, such as the GIC. Brown paper bag time, again. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/pgtable-3level.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index 6ef8afd1b64..86b8fe398b9 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -111,7 +111,7 @@
#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
#define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
#define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */
-#define L_PTE_S2_RDWR (_AT(pteval_t, 2) << 6) /* HAP[2:1] */
+#define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
/*
* Hyp-mode PL2 PTE definitions for LPAE.