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authorLinus Torvalds <torvalds@linux-foundation.org>2013-02-20 14:27:58 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2013-02-20 14:27:58 -0800
commit32f9aab8ebd886211a7b3e552753af014c3e5225 (patch)
treef95ca8b49a73c6c4baa8cf9d47c65db67a1f5f58 /arch/arm/include
parente177bb587ea0fade3d9a86f6667da8d89bea3607 (diff)
parent1b1c7409b75a8b62906b78b84c8469002072b738 (diff)
downloadlinux-32f9aab8ebd886211a7b3e552753af014c3e5225.tar.gz
Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-arm
Pull ARM updates (part one) from Russell King: - MMC patches from Ulf Hansson and Pawel Moll. These add support for DDR mode and the latest variant found on ARM Versatile Express, as well as a number of cleanups. - A fix for to improve the behaviour of ARMs sched_clock() - Changes to the ARM ioremap() code. I'm not convinced with the primary arguments for this, but it's been around for a while, and people seem happy with it - and the "other" justification for this is at http://lkml.org/lkml/2012/12/6/184 - Add SCHED_HRTICK to ARMs Kconfig - Making the ARM SHA/AES code Thumb-2 compatible - A collection of other small updates. * 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (26 commits) ARM: add SCHED_HRTICK config option ARM: 7650/1: mm: replace direct access to mm->context.id with new macro ARM: 7649/1: mm: mm->context.id fix for big-endian ARM: 7648/1: pci: Allow passing per-controller private data ARM: 7647/1: pci: Keep pci_common_init() around after init ARM: fix warnings introduced by previous patch ARM: 7646/1: mm: use static_vm for managing static mapped areas ARM: 7645/1: ioremap: introduce an infrastructure for static mapped area ARM: 7644/1: vmregion: remove vmregion code entirely MAINTAINERS: Re-assert MMCI driver maintainer status MAINTAINERS: add additional file for MMCI driver MAINTAINERS: add maintainer entry for AMBA serial drivers ARM: 7637/1: memory: use SZ_ constants for defining the virtual memory layout ARM: 7643/1: sched: correct update_sched_clock() ARM: 7635/1: versatile: fix the PCI IRQ regression ARM: 7639/1: cache-l2x0: add missed dummy outer_resume entry ARM: 7630/1: mmc: mmci: Fixup and cleanup code for DMA handling ARM: 7632/1: spinlock: avoid exclusive accesses on unlock() path ARM: 7631/1: mmc: mmci: Add new VE MMCI variant ARM: 7623/1: mmc: mmci: Fixup clock gating when freq is 0 for ST-variants ...
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/mach/pci.h1
-rw-r--r--arch/arm/include/asm/memory.h8
-rw-r--r--arch/arm/include/asm/outercache.h1
-rw-r--r--arch/arm/include/asm/spinlock.h16
4 files changed, 7 insertions, 19 deletions
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index db9fedb57f2..5cf2e979b4b 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -23,6 +23,7 @@ struct hw_pci {
#endif
struct pci_ops *ops;
int nr_controllers;
+ void **private_data;
int (*setup)(int nr, struct pci_sys_data *);
struct pci_bus *(*scan)(int nr, struct pci_sys_data *);
void (*preinit)(void);
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 1c4df27f933..64c770d2419 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -36,23 +36,23 @@
* TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
*/
#define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET)
-#define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(0x01000000))
+#define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(SZ_16M))
#define TASK_UNMAPPED_BASE ALIGN(TASK_SIZE / 3, SZ_16M)
/*
* The maximum size of a 26-bit user space task.
*/
-#define TASK_SIZE_26 UL(0x04000000)
+#define TASK_SIZE_26 (UL(1) << 26)
/*
* The module space lives between the addresses given by TASK_SIZE
* and PAGE_OFFSET - it must be within 32MB of the kernel text.
*/
#ifndef CONFIG_THUMB2_KERNEL
-#define MODULES_VADDR (PAGE_OFFSET - 16*1024*1024)
+#define MODULES_VADDR (PAGE_OFFSET - SZ_16M)
#else
/* smaller range for Thumb-2 symbols relocation (2^24)*/
-#define MODULES_VADDR (PAGE_OFFSET - 8*1024*1024)
+#define MODULES_VADDR (PAGE_OFFSET - SZ_8M)
#endif
#if TASK_SIZE > MODULES_VADDR
diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h
index 53426c66352..12f71a19042 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -92,6 +92,7 @@ static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
static inline void outer_flush_all(void) { }
static inline void outer_inv_all(void) { }
static inline void outer_disable(void) { }
+static inline void outer_resume(void) { }
#endif
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index b4ca707d0a6..6220e9fdf4c 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -119,22 +119,8 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
static inline void arch_spin_unlock(arch_spinlock_t *lock)
{
- unsigned long tmp;
- u32 slock;
-
smp_mb();
-
- __asm__ __volatile__(
-" mov %1, #1\n"
-"1: ldrex %0, [%2]\n"
-" uadd16 %0, %0, %1\n"
-" strex %1, %0, [%2]\n"
-" teq %1, #0\n"
-" bne 1b"
- : "=&r" (slock), "=&r" (tmp)
- : "r" (&lock->slock)
- : "cc");
-
+ lock->tickets.owner++;
dsb_sev();
}