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authorLinus Torvalds <torvalds@linux-foundation.org>2012-05-21 16:01:50 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2012-05-21 16:01:50 -0700
commitff8ce5f67ddca709fe59e6173f89260f0fdc2b22 (patch)
tree90d3ad380b290d251b54590be485b2ffb4528e5a /Documentation
parent4f6ade91532b5b05ea28219b891f12a3cec528cd (diff)
parent4ab1056766a4e49f6b9ef324313dd1583f8f8f4e (diff)
downloadlinux-ff8ce5f67ddca709fe59e6173f89260f0fdc2b22.tar.gz
Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-arm
Pull core ARM updates from Russell King: "This is the bulk of the core ARM updates for this merge window. Included in here is a different way to handle the VIVT cache flushing on context switch, which should allow scheduler folk to remove a special case in their core code. We have architectured timer support here, which is a set of timers specified by the ARM architecture for future SoCs. So we should see less variability in timer design going forward. The last big thing here is my cleanup to the way we handle PCI across ARM, fixing some oddities in some platforms which hadn't realised there was a way to deal with their private data already built in to our PCI backend. I've also removed support for the ARMv3 architecture; it hasn't worked properly for years so it seems pointless to keep it around." * 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (47 commits) ARM: PCI: remove per-pci_hw list of buses ARM: PCI: dove/kirkwood/mv78xx0: use sys->private_data ARM: PCI: provide a default bus scan implementation ARM: PCI: get rid of pci_std_swizzle() ARM: PCI: versatile: fix PCI interrupt setup ARM: PCI: integrator: use common PCI swizzle ARM: 7416/1: LPAE: Remove unused L_PTE_(BUFFERABLE|CACHEABLE) macros ARM: 7415/1: vfp: convert printk's to pr_*'s ARM: decompressor: avoid speculative prefetch from non-RAM areas ARM: Remove ARMv3 support from decompressor ARM: 7413/1: move read_{boot,persistent}_clock to the architecture level ARM: Remove support for ARMv3 ARM610 and ARM710 CPUs ARM: 7363/1: DEBUG_LL: limit early mapping to the minimum ARM: 7391/1: versatile: add some auxdata for device trees ARM: 7389/2: plat-versatile: modernize FPGA IRQ controller AMBA: get rid of last two uses of NO_IRQ ARM: 7408/1: cacheflush: return error to userspace when flushing syscall fails ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held ARM: 7404/1: cmpxchg64: use atomic64 and local64 routines for cmpxchg64 ARM: 7347/1: SCU: use cpu_logical_map for per-CPU low power mode ...
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/arm/arch_timer.txt27
1 files changed, 27 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
new file mode 100644
index 00000000000..52478c83d0c
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+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -0,0 +1,27 @@
+* ARM architected timer
+
+ARM Cortex-A7 and Cortex-A15 have a per-core architected timer, which
+provides per-cpu timers.
+
+The timer is attached to a GIC to deliver its per-processor interrupts.
+
+** Timer node properties:
+
+- compatible : Should at least contain "arm,armv7-timer".
+
+- interrupts : Interrupt list for secure, non-secure, virtual and
+ hypervisor timers, in that order.
+
+- clock-frequency : The frequency of the main counter, in Hz. Optional.
+
+Example:
+
+ timer {
+ compatible = "arm,cortex-a15-timer",
+ "arm,armv7-timer";
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ clock-frequency = <100000000>;
+ };