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authorBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2007-10-13 17:47:51 +0200
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2007-10-13 17:47:51 +0200
commit6e249395eace037ef139a1c8996b31e3797e412a (patch)
tree7b5df3653a47d49ff422124409760f3b33b74ccb
parent249aa4ff1778b318346d8ba4a7fa62c169a29410 (diff)
downloadlinux-6e249395eace037ef139a1c8996b31e3797e412a.tar.gz
pdc202xx_new: check ide_config_drive_speed() return value
Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
-rw-r--r--drivers/ide/pci/pdc202xx_new.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/ide/pci/pdc202xx_new.c b/drivers/ide/pci/pdc202xx_new.c
index 5fb1eedc819..95600681bd3 100644
--- a/drivers/ide/pci/pdc202xx_new.c
+++ b/drivers/ide/pci/pdc202xx_new.c
@@ -150,13 +150,13 @@ static int pdcnew_tune_chipset(ide_drive_t *drive, const u8 speed)
{
ide_hwif_t *hwif = HWIF(drive);
u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
- int err;
/*
* Issue SETFEATURES_XFER to the drive first. PDC202xx hardware will
* automatically set the timing registers based on 100 MHz PLL output.
*/
- err = ide_config_drive_speed(drive, speed);
+ if (ide_config_drive_speed(drive, speed))
+ return 1;
/*
* As we set up the PLL to output 133 MHz for UltraDMA/133 capable
@@ -212,7 +212,7 @@ static int pdcnew_tune_chipset(ide_drive_t *drive, const u8 speed)
set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
}
- return err;
+ return 0;
}
static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)