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authorHaojian Zhuang <haojian.zhuang@linaro.org>2014-04-02 21:31:50 +0800
committerArnd Bergmann <arnd@arndb.de>2014-07-26 12:14:32 +0200
commit28c9770bcbd2b6dbab99669825a2f8fa69e6d35b (patch)
tree9b91d44b0a7f16770749ee4f214ceb7498e79d32
parentbf1d9879ea7f53f652baea47e5ff071a6ade9708 (diff)
downloadlinux-28c9770bcbd2b6dbab99669825a2f8fa69e6d35b.tar.gz
ARM: dts: fix L2 address in Hi3620
Fix the address of L2 controler register in hi3620 SoC. This has been wrong from the point that the file was merged in v3.14. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Wei Xu <xuwei5@hisilicon.com> Cc: stable@vger.kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-rw-r--r--arch/arm/boot/dts/hi3620.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index ab1116d086b..83a5b8685bd 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -73,7 +73,7 @@
L2: l2-cache {
compatible = "arm,pl310-cache";
- reg = <0xfc10000 0x100000>;
+ reg = <0x100000 0x100000>;
interrupts = <0 15 4>;
cache-unified;
cache-level = <2>;