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authorSteve Capper <steve.capper@linaro.org>2014-06-27 11:05:57 +0100
committerSteve Capper <steve.capper@linaro.org>2014-06-27 11:33:57 +0100
commit1824b7baeff54280035470b0f57784f23f1e3018 (patch)
tree1bd801ed90f7e45031bacde56fb3aa22464af295
parent9580f7022362bf717457b6b73de1e0ed0fede211 (diff)
downloadlinux-for-broonie/icache-fix.tar.gz
arm64: mm: Make icache synchronisation logic huge page awarefor-broonie/icache-fix
The __sync_icache_dcache routine will only flush the dcache for the first page of a compound page, potentially leading to stale icache data residing further on in a hugetlb page. This patch addresses this issue by taking into consideration the order of the page when flushing the dcache. Reported-by: Mark Brown <broonie@kernel.org> Signed-off-by: Steve Capper <steve.capper@linaro.org>
-rw-r--r--arch/arm64/mm/flush.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c
index e4193e3adc7..0d64089d28b 100644
--- a/arch/arm64/mm/flush.c
+++ b/arch/arm64/mm/flush.c
@@ -79,7 +79,8 @@ void __sync_icache_dcache(pte_t pte, unsigned long addr)
return;
if (!test_and_set_bit(PG_dcache_clean, &page->flags)) {
- __flush_dcache_area(page_address(page), PAGE_SIZE);
+ __flush_dcache_area(page_address(page),
+ PAGE_SIZE << compound_order(page));
__flush_icache_all();
} else if (icache_is_aivivt()) {
__flush_icache_all();