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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 Linaro Ltd.
*/
#ifndef HISI_ISP_CSIPHY_H
#define HISI_ISP_CSIPHY_H
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <media/media-entity.h>
#include <media/v4l2-device.h>
#include <media/v4l2-mediabus.h>
#include <media/v4l2-subdev.h>
#define ISP_CSIPHY_PAD_SINK 0
#define ISP_CSIPHY_PAD_SRC 1
#define ISP_CSIPHY_PADS_NUM 2
/* CSI2IF Registers */
#define CSI2IF_VERSION_REG 0x0
#define CSI2IF_N_LANES_REG 0x4
#define CSI2IF_CSI2_RESETN_REG 0x8
#define CSI2IF_INT_ST_MAIN_REG 0xC
#define CSI2IF_DATA_IDS_1_REG 0x10
#define CSI2IF_PHY_SHUTDOWNZ_REG 0x40
#define CSI2IF_DPHY_RSTZ_REG 0x44
#define CSI2IF_PHY_RX_REG 0x48
#define CSI2IF_PHY_STOPSTATE_REG 0x4C
#define CSI2IF_PHY_TEST_CTRL0_REG 0x50
#define CSI2IF_PHY_TEST_CTRL1_REG 0x54
#define CSI2IF_PHY_CAL_REG 0xCC
#define CSI2IF_INT_ST_PHY_FATAL_REG 0xE0
#define CSI2IF_INT_MSK_PHY_FATAL_REG 0xE4
#define CSI2IF_INT_FORCE_PHY_FATAL_REG 0xE8
#define CSI2IF_INT_ST_PKT_FATAL_REG 0xF0
#define CSI2IF_INT_MSK_PKT_FATAL_REG 0xF4
#define CSI2IF_INT_FORCE_PKT_FATAL_REG 0xF8
#define CSI2IF_INT_ST_FRAME_FATAL_REG 0x100
#define CSI2IF_INT_MSK_FRAME_FATAL_REG 0x104
#define CSI2IF_INT_FORCE_FRAME_FATAL_REG 0x108
#define CSI2IF_INT_ST_PHY_REG 0x110
#define CSI2IF_INT_MSK_PHY_REG 0x114
#define CSI2IF_INT_FORCE_PHY_REG 0x118
#define CSI2IF_INT_ST_PKT_REG 0x120
#define CSI2IF_INT_MSK_PKT_REG 0x124
#define CSI2IF_INT_FORCE_PKT_REG 0x128
#define CSI2IF_INT_ST_LINE_REG 0x130
#define CSI2IF_INT_MSK_LINE_REG 0x134
#define CSI2IF_INT_FORCE_LINE_REG 0x138
/* CSI2IF_PHY_STOPSTATE_REG Register bits */
#define CSI2IF_PHY_STOPSTATEDATA_0_OFFSET 0
#define CSI2IF_PHY_STOPSTATEDATA_0_LEN 1
#define CSI2IF_PHY_STOPSTATECLK_OFFSET 16
#define CSI2IF_PHY_STOPSTATECLK_LEN 1
#define CSI2IF_PHY_RXCLKACTIVEHS_OFFSET 17
#define CSI2IF_PHY_RXCLKACTIVEHS_LEN 1
#define CSI_INDEX_CNT (3)
#define CFG_CLK_ATTR (0x01)
#define CFG_CLK_DETECT (0x0A)
#define CFG_DESKEW_1 (0x0B)
#define CFG_DESKEW_2 (0x0F)
#define LANE0_SETTLE (0x30)
#define LANE0_MISC (0x31)
#define LANE0_ADDITION (0x32)
#define LANE0_DESKEW_1 (0x3A)
#define LANE0_DESKEW_2 (0x3B)
#define LANE0_DESKEW_3 (0x3C)
#define LANE1_SETTLE (0x40)
#define LANE1_MISC (0x41)
#define LANE1_ADDITION (0x42)
#define LANE1_DESKEW_1 (0x4A)
#define LANE1_DESKEW_2 (0x4B)
#define LANE1_DESKEW_3 (0x4C)
#define LANE2_SETTLE (0x50)
#define LANE2_MISC (0x51)
#define LANE2_ADDITION (0x52)
#define LANE2_DESKEW_1 (0x5A)
#define LANE2_DESKEW_2 (0x5B)
#define LANE2_DESKEW_3 (0x5C)
#define LANE3_SETTLE (0x60)
#define LANE3_MISC (0x61)
#define LANE3_ADDITION (0x62)
#define LANE3_DESKEW_1 (0x6A)
#define LANE3_DESKEW_2 (0x6B)
#define LANE3_DESKEW_3 (0x6C)
struct csiphy_lane {
u8 pos;
u8 pol;
};
struct csiphy_lanes_cfg {
int num_data;
struct csiphy_lane *data;
struct csiphy_lane clk;
};
struct csiphy_csi2_cfg {
struct csiphy_lanes_cfg lane_cfg;
};
struct csiphy_config {
u8 combo_mode;
u8 csid_id;
struct csiphy_csi2_cfg *csi2;
};
struct csiphy_device;
struct csiphy_hw_ops {
void (*csi2_enable)(struct csiphy_device *csiphy,
struct csiphy_config *cfg);
void (*csi2_disable)(struct csiphy_device *csiphy,
struct csiphy_config *cfg);
};
struct csiphy_device {
struct isp *isp;
u8 id;
struct v4l2_subdev subdev;
struct media_pad pads[ISP_CSIPHY_PADS_NUM];
void __iomem *base;
u32 irq;
char irq_name[30];
struct isp_clock *clock;
int nclocks;
struct csiphy_config cfg;
struct v4l2_mbus_framefmt fmt[ISP_CSIPHY_PADS_NUM];
const struct csiphy_hw_ops *ops;
const struct csiphy_format *formats;
unsigned int nformats;
};
struct resources;
int isp_csiphy_subdev_init(struct isp *isp,
struct csiphy_device *csiphy,
const struct resources *res, u8 id);
int isp_csiphy_register_entity(struct csiphy_device *csiphy,
struct v4l2_device *v4l2_dev);
void isp_csiphy_unregister_entity(struct csiphy_device *csiphy);
#endif /* HISI_ISP_CSIPHY_H */
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